7132LA20JG IDT, 7132LA20JG Datasheet
7132LA20JG
Specifications of 7132LA20JG
Related parts for 7132LA20JG
7132LA20JG Summary of contents
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... R/W L NOTES: 1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω. IDT7142 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270Ω. ©2010 Integrated Device Technology, Inc. HIGH SPEED DUAL PORT STATIC RAM ◆ ◆ ◆ ◆ ◆ ...
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... High Speed Dual Port Static RAM Description The IDT7132/IDT7142 are high-speed Dual-Port Static RAMs. The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM “MASTER” Dual-Port RAM together with the IDT7142 “SLAVE” Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/ ...
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... Recommended DC Operating Conditions Symbol V Supply Voltage CC > Vcc + 10%. TERM GND Ground V Input High Voltage IH V Input Low Voltage IL NOTES (min.) = -1.5V for pulse width less than 10ns must not exceed Vcc + 10%. TERM 3 6. ...
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... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE I Dynamic Operating Current CC (Both Ports Active) Outputs Disabled Standby Current SB1 (Both Ports - TTL Level Inputs) ...
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... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL Open Drain Output V OL Low Voltage (BUSY) ...
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... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5V DATA OUT 775Ω *100pF for 55 and 100ns versions Figure 1. AC Output Test Load ...
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... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time ...
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... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM Timing Waveform of Read Cycle No. 1, Either Side ADDRESS t OH DATA PREVIOUS DATA VALID OUT BUSY OUT Timing Waveform of Read Cycle No. 2, Either Side CE OE DATA OUT I CC CURRENT I SS NOTES: ...
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... WC BAA LOW during a R/W controlled write cycle, the write pulse width must be the larger High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t bus for the required ...
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... This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2 LOW during a R/W controlled write cycle, the write pulse width must be the larger HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t ...
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... WH t Write Data Valid to Read Data Delay DDD (3) t Arbitration Priority Set-up Time APS BUSY Disable to Valid Data (4) t BDD BUSY Timing (For Slave IDT7142 Only) Write to BUSY Input ( Write Hold After BUSY ( (2) t Write Pulse to Data Delay WDD ...
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... Timing Waveform of Write with BUSY R/W "A" BUSY "B" R/W "B" NOTES: must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master BUSY is asserted on port "B" blocking R/W "B" applies only to the slave version (IDT7142 All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port " ...
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... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM Timing Waveform of BUSY Arbitration Controlled by CE Timing ADDR and "A" "B" CE "B" (2) t APS CE "A" BUSY "A" Timing Waveform of BUSY Arbitration Controlled by Address Match Timing ...
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... BUSY signal as a write inhibit signal. Thus on the IDT7132/ 2692 tbl 13 IDT7142 SRAMs the BUSY pin is an output if the part is Master (IDT7132), and the BUSY pin is an input if the part is a Slave (IDT7142) as shown in Figure 3. or BUSY = LOW will ...
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... Commercial & Military LA Low Power SA Standard Power 7132 16K (2K x 8-Bit) MASTER Dual-Port RAM 7142 16K (2K x 8-Bit) SLAVE Dual-Port RAM Changed drawing format Changed Busy Logic and Width Expansion copy parameter A 15 6.42 , ⎫ ⎬ Speed in nanoseconds ⎭ 2692 drw 16 ...
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... Page 14 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Military, Industrial and Commercial Temperature Ranges Corrected errors in Figure 3 by changing 1250 Clarified Industrial temp offering for 25ns Removed INT from V ...