7132LA20JG IDT, 7132LA20JG Datasheet - Page 11

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7132LA20JG

Manufacturer Part Number
7132LA20JG
Description
SRAM
Manufacturer
IDT
Series
IDT7132SA/LAr
Type
Dual Port RAMr
Datasheet

Specifications of 7132LA20JG

Product Category
SRAM
Rohs
yes
Memory Size
16 Kbit
Organization
2 K x 8
Access Time
20 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Current
200 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
PLCC-52
Interface
TTL
Memory Type
Asynchronous
Part # Aliases
IDT7132LA20JG
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. t
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
BUSY Timing (For Master IDT7132 Only)
t
t
t
t
t
t
t
t
t
BUSY Timing (For Slave IDT7142 Only)
t
t
t
t
BUSY Timing (For Master IDT7132 Only)
t
t
t
t
t
t
t
t
t
BUSY Timing (For Slave IDT7142 Only)
t
t
t
t
BAA
BDA
BAC
BDC
WDD
WH
DDD
APS
BDD
WB
WH
WDD
DDD
BAA
BDA
BAC
BDC
WDD
WH
DDD
APS
BDD
WB
WH
WDD
DDD
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Symbol
Symbol
BDD
is a calculated parameter and is the greater of 0, t
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay
Write Hold After BUSY
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
Write to BUSY Input
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay
Write Hold After BUSY
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
Write to BUSY Input
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
(5)
(5)
(6)
(6)
(6)
(6)
(2)
(2)
(2)
(2)
(4)
(4)
(3)
(3)
Parameter
(2)
(2)
(2)
(2)
WDD
Parameter
– t
WP
(actual) or t
DDD
6.42
– t
11
DW
(actual).
Military, Industrial and Commercial Temperature Ranges
Min.
____
____
____
____
____
____
____
____
____
12
12
Com'l Only
5
0
7132X20
7142X20
Max.
(1)
(1)
____
____
____
____
20
20
20
20
50
35
25
40
30
(7,8)
Min.
Min.
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
20
20
15
15
5
0
5
0
Com'l, Ind
7132X25
7142X25
& Military
7132X55
7142X55
Com'l &
Military
Max.
Max.
(2)
(2)
____
____
____
____
____
____
____
____
30
30
30
30
80
55
50
80
55
20
20
20
20
50
35
35
50
35
Min.
Min.
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
20
20
20
20
5
0
5
0
7132X100
7142X100
Com'l &
7132X35
7142X35
Com'l &
Military
Military
Max.
Max.
120
100
120
100
____
____
____
____
50
50
50
50
65
____
____
____
____
20
20
20
20
60
35
35
60
35
2692 tbl 11b
2692 tbl 11a
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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