7132LA20JG IDT, 7132LA20JG Datasheet - Page 13

• Manufacturer Part Number: 7132LA20JG
• Description: SRAM
• Manufacturer: IDT
• Series: IDT7132SA/LAr
• Type: Dual Port RAMr

Specifications of 7132LA20JG

• Product Category: SRAM
• Rohs: yes
• Memory Size: 16 Kbit
• Organization: 2 K x 8
• Access Time: 20 ns
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Current: 200 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-52
• Interface: TTL
• Memory Type: Asynchronous
• Part # Aliases: IDT7132LA20JG

"A"
Timing Waveform of BUSY Arbitration Controlled by CE Timing
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t
Truth Tables
Table I. Non-Contention Read/Write Control
NOTES:
1. A
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
4. 'H' = V
ADDR
ADDR
BUSY
BUSY
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
R/W
and
ADDR
X
X
X
L
H
CE
CE
0L
APS
- A
"A"
"B"
"B"
"B"
"A"
"B"
"A"
is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
IH
10L
, 'L' = V
Left or Right Port
CE
≠ A
H
H
L
L
L
0R
IL
- A
, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
t
10R
APS
OE
X
X
X
H
L
(2)
(1)
DATA
DATA
D
t
Z
Z
Z
APS
0-7
OUT
IN
(2)
WDD
ADDRESSES MATCH
t
and t
Port Disabled and in Power-Down Mode, I
Data on Port Written into Memory
Data in Memory Output on Port
High Impedance Outputs
CE
BAA
R
t
DDD
RC
= CE
t
timing.
BAC
or t
(1)
L
= V
WC
IH,
Power-Down Mode, I
ADDRESSES MATCH
6.42
(3)
13
(2)
SB1
Military, Industrial and Commercial Temperature Ranges
SB2
or I
t
BDC
or I
SB3
ADDRESSES DO NOT MATCH
(4)
SB4
Function
t
BDA
(1)
2692 drw 14
2692 drw 13
2692 tbl 12