MAX6745XKVD3+T Maxim Integrated, MAX6745XKVD3+T Datasheet - Page 10

• Manufacturer Part Number: MAX6745XKVD3+T
• Description: Supervisory Circuits MCU Supervisor
• Manufacturer: Maxim Integrated
• Series: MAX6736, MAX6737, MAX6738, MAX6739, MAX6740, MAX6741, MAX6742, MAX6743, MAX6744, MAX6745r

Specifications of MAX6745XKVD3+T

• Rohs: yes
• Number Of Voltages Monitored: 2
• Monitored Voltage: 1.8 V to 5 V, 0.9 V to 3.3 V
• Undervoltage Threshold: 1.53 V, 0.765 V
• Overvoltage Threshold: 1.62 V, 0.81 V
• Output Type: Active Low, Push-Pull
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 225 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SC-70
• Chip Enable Signals: No
• Maximum Power Dissipation: 247 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Supply Current (typ): 5 uA, 10 uA
• Supply Voltage - Min: 1 V

MAXQ613
16-Bit Microcontroller with Infrared Module
10
BARE DIE
10
11
12
17
18
22
23
24
26
28
30
31
32
33
34
—
—
7
8
9
32 TQFN-
PIN
EP
10
11
12
16
17
20
21
24
25
26
27
23
—
—
—
—
—
7
8
9
2, 4, 15, 16,
30, 31, 36,
44 TQFN-
EP
10
11
12
13
14
21
22
25
26
27
29
32
33
34
35
38
39
37
—
9
P0.6/TBB0/
P0.7/TBB1/
P2.2/SCLK
P2.0/MOSI
P2.1/MISO
P2.3/SSEL
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/INT4
P1.5/INT5
P1.6/INT6
P1.7/INT7
P2.7/TDO
P2.4/TCK
P2.6/TMS
P2.5/TDI
NAME
INT14
INT15
N.C.
EP
NO CONNECTION PINS
Port 1 General-Purpose, Digital I/O Pins with Interrupt Capability. These
port pins function as general-purpose I/O pins with their input and
output states controlled by the PD1, PO1, and PI1 registers. All port pins
default to high-impedance mode after a reset. Software must configure
these pins after release from reset to remove the high-impedance
condition. All external interrupts must be enabled from software before
they can be used.
Port 2 General-Purpose, Digital I/O Pins. These port pins function as
general-purpose I/O pins with their input and output states controlled
by the PD2, PO2, and PI2 registers. All port pins default to high-
impedance mode after a reset. Software must configure these pins after
release from reset to remove the high-impedance condition. All special
functions must be enabled from software before they can be used.
No Connection. Not internally connected.
Exposed Pad. Connect EP directly to the ground plane.
GPIO PORT PIN
GPIO PORT PIN
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Pin Description (continued)
FUNCTION
SPI: Active-Low Slave Select
Type B Timer 0 Pin B/INT14
Type B Timer 1 Pin B/INT15
EXTERNAL INTERRUPT
SPI: Master Out-Slave In
SPI: Master In-Slave Out
JTAG: Test Mode Select
SPECIAL FUNCTION
JTAG: Test Data Out
JTAG: Test Data In
JTAG: Test Clock
SPI: Slave Clock
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
Maxim Integrated