MT45W1MW16BDGB-708 AT TR Micron Technology Inc, MT45W1MW16BDGB-708 AT TR Datasheet - Page 26

IC PSRAM 16MBIT 70NS 54VFBGA

MT45W1MW16BDGB-708 AT TR

Manufacturer Part Number
MT45W1MW16BDGB-708 AT TR
Description
IC PSRAM 16MBIT 70NS 54VFBGA
Manufacturer
Micron Technology Inc

Specifications of MT45W1MW16BDGB-708 AT TR

Format - Memory
RAM
Memory Type
PSRAM (Page)
Memory Size
16M (1M x 16)
Speed
70ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-30°C ~ 85°C
Package / Case
54-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1419-2
Figure 20:
Latency Counter (BCR[13:11]) Default = Three-Clock Latency
Operating Mode (BCR[15]) Default = Asynchronous Operation
Table 5:
Figure 21:
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
Latency Configuration Code
2 (3 clocks)
3 (4 clocks) – default
DQ[15:0]
DQ[15:0]
DQ[15:0]
A[19:0]
WAIT
WAIT
ADV#
CLK
CLK
Latency Configuration
V
V
V
V
V
V
V
V
V
V
WAIT Configuration During Burst Operation
Latency Counter
IH
IL
IH
IL
IH
IL
OH
OL
OH
OL
Note:
ADDRESS
VALID
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. Only latency code two
(three clocks) or latency code three (four clocks) is allowed (see Table 5 and Figure 21).
The operating mode bit selects either synchronous BURST operation or the default
asynchronous mode of operation.
Non-default BCR setting for WAIT during BURST operation: WAIT active LOW.
Code 3
Code 2
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
D[0]
(Default)
D[1]
26
OUTPUT
VALID
104 (9.62ns)
104 MHz
66 (15ns)
D[2]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Max Input CLK Frequency (MHz)
OUTPUT
OUTPUT
VALID
VALID
D[3]
OUTPUT
OUTPUT
VALID
VALID
DON’T CARE
Configuration Registers
DON’T CARE
D[4]
©2005 Micron Technology, Inc. All rights reserved.
OUTPUT
OUTPUT
VALID
VALID
53 (18.75ns)
80 (12.50ns)
BCR[8] = 0
Data valid in current cycle.
BCR[8] = 1
Data valid in next cycle.
80 MHz
UNDEFINED
OUTPUT
OUTPUT
VALID
VALID

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