IS42S16400F-6TL ISSI, Integrated Silicon Solution Inc, IS42S16400F-6TL Datasheet - Page 8

• Manufacturer Part Number: IS42S16400F-6TL
• Description: IC SDRAM 64MBIT 166MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16400F-6TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6 ns, 5.4 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1075; IS42S16400F-6TL

IS42S16400F
IC42S16400F
8
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
11. Does not affect the state of the bank and acts as a NOP to that bank.
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands,
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-
mands to the other bank are determined by its current state and CURRENT STATE BANK n truth tables.
applied on each positive clock edge during these states.
READs or WRITEs with auto precharge disabled.
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when t
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when t
Row Activating: Starts with registration of an ACTIVE command and ends when t
Accessing Mode
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when t
Read w/Auto
Precharging: Starts with registration of a PRECHARGE command and ends when t
Write w/Auto
Row Active: A row in the bank has been activated, and t
Refreshing: Starts with registration of an AUTO REFRESH command and ends when t
Register: Starts with registration of a LOAD MODE REGISTER command and ends when t
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
Idle: The bank has been precharged, and t
accesses are in progress.
nated.
nated.
will be in the idle state.
be in the row active state.
met. Once t
met. Once t
SDRAM will be in the all banks idle state.
t
banks will be in the idle state.
mrD
is met, the SDRAM will be in the all banks idle state.
rp
rp
is met, the bank will be in the idle state.
is met, the bank will be in the idle state.
rp
has been met.
rcD
has been met. No data bursts/accesses and no register
Integrated Silicon Solution, Inc. — www.issi.com
rcD
is met. Once t
rp
is met. Once t
rc
rp
is met. Once t
is met. Once t
mrD
rcD
has been met. Once
rp
is met, the bank will
is met, the bank
rp
rc
rp
rp
has been
is met, the
is met, all
has been
03/19/08
Rev. A