IS42S16400F-6TL ISSI, Integrated Silicon Solution Inc, IS42S16400F-6TL Datasheet - Page 9

• Manufacturer Part Number: IS42S16400F-6TL
• Description: IC SDRAM 64MBIT 166MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16400F-6TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6 ns, 5.4 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1075; IS42S16400F-6TL

IS42S16400F
IC42S16400F
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m
NOTE:
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
03/19/08
3. Current state definitions:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after t
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled
CURRENT STATE
Any
Idle
Row
Activating,
Active, or
Precharging
Read
(Auto
Precharge
Disabled)
Write
(Auto
Precharge
Disabled)
Read
(With Auto
Precharge)
Write
(With Auto
Precharge)
ous state was self refresh).
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Excep-
tions are covered in the notes below.
only.
and READs or WRITEs with auto precharge disabled.
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when t
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when t
Read w/Auto
Write w/Auto
Row Active: A row in the bank has been activated, and t
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
Idle: The bank has been precharged, and t
accesses are in progress.
nated.
nated.
met. Once t
met. Once t
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
rp
rp
is met, the bank will be in the idle state.
is met, the bank will be in the idle state.
(9)
(9)
(9)
(9)
rp
has been met.
rcD
has been met. No data bursts/accesses and no register
(7)
(7,12)
(7,8,16)
(7)
(7,11)
(7,8,15)
(7,10)
(7,8,14)
(7,13)
(7,8,17)
(1-6)
xsr
has been met (if the previ-
CS RAS CAS WE
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
rp
rp
has been
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
has been
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
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