IS42S32160A-75BL ISSI, Integrated Silicon Solution Inc, IS42S32160A-75BL Datasheet - Page 12

• Manufacturer Part Number: IS42S32160A-75BL
• Description: IC SDRAM 512MBIT 133MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32160A-75BL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-BGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 14b
• Access Time (max): 6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: Mini BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 185mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1061

6
IS42S32160A
12
Concurrent Auto Precharge
An access command (READ or WRITE) to another bank while an access command with auto precharge enabled
is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE.
ICSI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
READ with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n,
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n
CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is regis-tered.
when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered.
Internal
States
Internal
States
NOTE: 1. DQM is HIGH at T2 to prevent D
NOTE: DQM is LOW.
READ With Auto Precharge Interrupted by a WRITE
READ With Auto Precharge Interrupted by a READ
COMMAND
ADDRESS
BANK m
COMMAND
BANK n
ADDRESS
BANK m
BANK n
CLK
DQM
DQ
CLK
DQ
1
Active
Page
READ - AP
Page Active
BANK n,
T0
NOP
BANK n
COL a
T0
READ with Burst of 4
CAS Latency = 3 (BANK n)
READ - AP
Page Active
BANK n,
Page Active
BANK n
T1
NOP
COL a
T1
OUT
READ with Burst of 4
CAS Latency = 3 (BANK n)
-a+1 from contending with D
T2
NOP
T2
NOP
T3
D
NOP
OUT
a
BANK m,
READ - AP
T3
BANK m
COL d
Interrupt Burst, Precharge
CAS Latency = 3 (BANK m)
READ with Burst of 4
BANK m,
WRITE - AP
COL d
BANK m
T4
D
d
IN
IN
Interrupt Burst, Precharge
WRITE with Burst of 4
-d at T4.
T4
NOP
D
T5
OUT
a
t
RP - BANK n
d + 1
NOP
D
IN
t
RP - BANK n
T5
NOP
T6
D
a + 1
d + 2
NOP
D
OUT
IN
DON’T CARE
T6
NOP
T7
t WR - BANK m
d + 3
NOP
D
D
IN
OUT
Write-Back
d
Idle
DON T CARE
Integrated Silicon Solution, Inc.
Idle
T7
NOP
t RP - BANK m
Precharge
D
d + 1
OUT
Rev. 00E
07/21/09