IS42S32160A-75BL ISSI, Integrated Silicon Solution Inc, IS42S32160A-75BL Datasheet - Page 17

• Manufacturer Part Number: IS42S32160A-75BL
• Description: IC SDRAM 512MBIT 133MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32160A-75BL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-BGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 14b
• Access Time (max): 6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: Mini BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 185mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1061

I
IS42S32160A
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00E
07/21/09
•
•
This bit is used to select the burst write length.
8
9
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to “00”in normal operation.
Write Burst Length (A9)
No-Operation command
(RAS#=”H”,CAS#=”H”,WE#=”H”)
is Low).This prevents unwanted commands from being registered during idle or wait states.
Burst Stop command
(RAS#=”H”,CAS#=”H”,WE#=”L”)
The Burst Stop command is used to terminate either fixed-length or full-page bursts.This
command is only effective in a read/write burst without the auto precharge function.The terminated
read burst ends after a delay equal to the CAS#latency (refer to the following figure).The
termination of a write burst is shown in the following figure.
CAS# latency=2
tCK2,DQ’s
CL K
COMMAN D
CAS# latency=2,3
DQ’s
CLK
COMMAND
CAS# latency=3
tCK3,DQ’s
Termination of a Burst Read Operation (Burst Length > 4,CAS#Latency =2,3)
A9
0
1
A8
0
0
1
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
READ A
T0
T0
Termination of a Burst Write Operation (Burst Length =X)
NOP
Write Burst Length
Burst
Single Bit
A7
0
1
X
WRITE A
DIN A 0
T 1
T 1
NOP
Test Mode
normal mode
Vendor Use Only
Vendor Use Only
DOUT A 0
DIN A 1
T2
NOP
T2
NOP
DOUT A 0
DOUT A 1
DIN A 2
T3
NOP
T3
NOP
Input Data for the Write is masked.
Burst Stop
Burst Stop
don’t care
DOUT A 2
DOUT A 1
T4
T4
DOUT A 2
DOUT A 3
T5
NOP
The Burst ends after a delay equal to the CAS# latency.
T5
NOP
DOUT A 3
T6
NOP
T6
NOP
T7
NOP
T7
NOP
I
NOP
T 8
NOP
T 8
®
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