Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 112
Z8F011ASH020EG2156
Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet
1.Z8F011AHJ020EG2156.pdf
(257 pages)
Specifications of Z8F011ASH020EG2156
Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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PS025113-1212
Watchdog Timer Reload Unlock Sequence
WDT Reset in Normal Operation
If configured to generate a reset when a time-out occurs, the Watchdog Timer forces the
device into the System Reset state. The WDT status bit in the Watchdog Timer Control
Register is set to 1. See the
information about system reset operations.
WDT Reset in STOP Mode
If configured to generate a reset when a time-out occurs and the device is in STOP Mode,
the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the
STOP bit in the Watchdog Timer Control Register are set to 1 following WDT time-out in
STOP Mode. See the
mation about Stop Mode Recovery operations.
Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control Register
address, unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH and
WDTL) to allow changes to the time-out period. These write operations to the WDTCTL
Register address produce no effect on the bits in the WDTCTL Register. The locking
mechanism prevents spurious writes to the reload registers.
The following sequence is required to unlock the Watchdog Timer Reload Byte registers
(WDTU, WDTH and WDTL) for write access:
1. Write
2. Write
3. Write the Watchdog Timer Reload Upper Byte Register (WDTU).
4. Write the Watchdog Timer Reload High Byte Register (WDTH).
5. Write the Watchdog Timer Reload Low Byte Register (WDTL).
All three Watchdog Timer Reload registers must be written in the order listed above.
There must be no other register writes between each of these operations. If a register write
occurs, the lock state machine resets and no further writes can occur unless the sequence is
restarted. The value in the Watchdog Timer Reload registers is loaded into the counter
when the Watchdog Timer is first enabled and every time a WDT instruction is executed.
55H
AAH
to the Watchdog Timer Control Register (WDTCTL).
to the Watchdog Timer Control Register (WDTCTL).
Reset and Stop Mode Recovery
Reset and Stop Mode Recovery
chapter on page 21 for more infor-
Z8 Encore!
chapter on page 21 for more
Product Specification
®
F0830 Series
Operation
94
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