W7100A-64QFN WIZnet, W7100A-64QFN Datasheet

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W7100A-64QFN

Manufacturer Part Number
W7100A-64QFN
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet

Specifications of W7100A-64QFN

Rohs
yes
Interface Type
UART

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Internet Embedded MCU W7100A
Datasheet
Version 1.12
© 2011 WIZnet Co., Inc. All Rights Reserved.
For more information, visit our website at
http://www.wiznet.co.kr
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© Copyright 2011 WIZnet Co., Inc. All rights reserved.
Ver. 1.12

Related parts for W7100A-64QFN

W7100A-64QFN Summary of contents

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... Internet Embedded MCU W7100A © 2011 WIZnet Co., Inc. All Rights Reserved. For more information, visit our website at © Copyright 2011 WIZnet Co., Inc. All rights reserved. Datasheet Version 1.12 http://www.wiznet.co. Ver. 1.12 ...

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... Table of Contents 1 Overview ..................................................................................... 11 1.1 Introduction .................................................................................. 11 1.2 W7100A Features ............................................................................ 11 1.3 W7100A Block Diagram & Features ....................................................... 12 1.3.1 ALU (Arithmetic Logic Unit) ....................................................... 12 1.3.2 TCPIPCore ............................................................................ 14 1.4 Pin Description .............................................................................. 16 1.4.1 Pin Layout ............................................................................ 16 1.4.2 Pin Description ....................................................................... 17 1.4.2.1 Configuration ................................................................... 18 1.4.2.2 Timer ............................................................................ 19 1.4.2.3 UART ............................................................................. 19 1.4.2.4 DoCD™ Compatible Debugger ................................................ 19 1.4.2.5 Interrupt / Clock .............................................................. 19 1.4.2.6 GPIO ............................................................................. 20 1.4.2.7 Media Interface ................................................................ 21 1.4.2.8 Network Indicator LED ........................................................ 22 1.4.2.9 Power Supply Signal ........................................................... 22 1.5 64pin package description ................................................................. 24 1 ...

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... Mode3, 9-Bit UART, Variable Baud Rate, Timer1 or 2 Clock Source ................. 65 6.6 Examples of Baud Rate Setting ........................................................... 65 7 Watchdog Timer ............................................................................. 66 7.1 Overview ..................................................................................... 66 7.2 Interrupts ..................................................................................... 66 7.3 Watchdog Timer Reset ...................................................................... 67 7.4 Simple Timer ................................................................................. 68 7.5 System Monitor .............................................................................. 68 7.6 Watchdog Related Registers ............................................................... 68 7.7 Watchdog Control ........................................................................... 69 7.7.1 Clock Control ......................................................................... 70 © Copyright 2011 WIZnet Co., Inc. All rights reserved. 3 Ver. 1.12 ...

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... Crystal Characteristics ................................................................... 140 10.6 Transformer Characteristics ............................................................. 141 11 IR Reflow Temperature Profile (Lead-Free) ........................................... 142 12 Package Descriptions ..................................................................... 143 12.1 Package type: LQFP 100 .................................................................. 143 12.2 Package type: QFN 64 .................................................................... 145 13 Appendix:Performance Improvement about W7100A ................................ 147 13.1 Summary .................................................................................... 147 13.2 8–Bit Arithmetic Functions ............................................................... 147 13.2.1 Addition ............................................................................. 147 13.2.2 Subtraction ......................................................................... 149 13.2.3 Multiplication ...................................................................... 150 13.2.4 Division .............................................................................. 150 © ...

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... Arithmetic Functions ............................................................. 150 13.3.1 Addition ............................................................................. 150 13.3.2 Subtraction ......................................................................... 151 13.3.3 Multiplication ...................................................................... 151 13.4 32-bit Arithmetic Functions ............................................................. 152 13.4.1 Addition ............................................................................. 152 13.4.2 Subtraction ......................................................................... 153 13.4.3 Multiplication ...................................................................... 153 © Copyright 2011 WIZnet Co., Inc. All rights reserved. 5 Ver. 1.12 ...

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... Figure 1.3 B Register ....................................................................................... 13 Figure 1.4 Program Status Word Register ............................................................... 13 Figure 1.5 PSW Register ................................................................................... 13 Figure 1.6 TCPIPCore Block Diagram .................................................................... 14 Figure 1.7 W7100A Pin Layout ............................................................................ 16 Figure 1.8 W7100A QFN 64 Pin Layout ................................................................... 17 Figure 1.9 Power Design ................................................................................... 24 Figure 2.1 Code / Data Memory Connections .......................................................... 26 Figure 2.2. Boot Sequence Flowchart ................................................................... 27 Figure 2.3 APP Entry Process .............................................................................. 27 Figure 2.4 Changing the code memory Status ‘0’ ........................................... 28 Figure 2.5 Data Memory Map ............................................................................. 29 Figure 2.6 Standard 8051 External Pin Access Mode (EM[2:0] = “ ...

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... Figure 2.27 Second Byte of Internal Memory Wait States Register ................................. 38 Figure 2.28 Stack Pointer Register ....................................................................... 39 Figure 2.29 PHY Status Register .......................................................................... 39 Figure 2.30 Internal PHY Configuration Register ...................................................... 39 Figure 2.31 W7100A Configuration Register ............................................................ 40 Figure 2.32 Core clock count register ................................................................... 40 Figure 2.33 Core clock count register ................................................................... 41 Figure 2.34 Core clock count register ................................................................... 41 Figure 2.35 Core clock count register ................................................................... 41 Figure 3 ...

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... Figure 9.3 “TCP SERVER” Operation Flow ............................................................ 114 Figure 9.4 “TCP CLIENT” Operation Flow ............................................................. 121 Figure 9.5 UDP Operation Flow ......................................................................... 122 Figure 9.6 The received UDP data format ............................................................ 124 Figure 9.7 IPRAW Operation Flow ...................................................................... 131 Figure 9.8 The received IPRAW data format ......................................................... 132 © Copyright 2011 WIZnet Co., Inc. All rights reserved. 8 Ver. 1.12 ...

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... Figure 9.9 MACRAW Operation Flow ................................................................... 133 Figure 9.10 The received MACRAW data format ..................................................... 134 © Copyright 2011 WIZnet Co., Inc. All rights reserved. 9 Ver. 1.12 ...

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... Table 2.3 DPTR0, DPTR1 Operations ..................................................................... 36 Table 2.4 MD[2:0] Bit Values .............................................................................. 37 Table 2.5 Ram WTST Bit Values ........................................................................... 37 Table 2.6 TCPIPCore / Flash WTST Bit Values .......................................................... 37 Table 3.1 External Interrupt Pin Description ........................................................... 43 Table 3.2 W7100A Interrupt Summary ................................................................... 43 Table 4.1 I/O Ports Pin Description ...................................................................... 47 Table 4.2 Read-Modify-Write Instructions ............................................................... 48 Table 5.1 Timers 0, 1 Pin Description ................................................................... 50 Table 5.2 Timers 0, 1 Mode ............................................................................... 50 Table 5 ...

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... Overview 1.1 Introduction iMCU W7100A is the one-chip solution which integrates an 8051 compatible microcontroller, 64KB SRAM and hardwired TCP/IP Core for high performance and easy development. The TCP/IP core is a market-proven hardwired TCP/IP stack with an integrated Ethernet MAC & PHY. The Hardwired TCP/IP stack supports the TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE which has been used in various applications for years ...

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... W7100A Block Diagram & Features The W7100A internal block diagram is shown in the Figure 1.1. Details of block functions are described as follows: ALU – Performs arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), B registers, and related logics such as arithmetic unit, logic unit, multiplier, and divider. SFR – ...

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... OV Overflow flag F1 General purpose flag 1 P Parity flag The PSW register contains several bits that can reflect the current state of MCU. © Copyright 2011 WIZnet Co., Inc. All rights reserved. ACC (0xE0 ACC.4 ACC.3 ACC.2 Figure 1.2 Accumulator A Register B (0xF0) ...

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... TCPIPCore Figure 1.6 TCPIPCore Block Diagram Ethernet PHY The W7100A includes 10BaseT/100BaseTX Ethernet PHY. It supports half-duplex/full-duplex, auto-negotiation and auto-MDI/MDIX. It also supports 6 network indicator LED outputs such as Link, TX, RX status, Collision, speed and duplex. TCPIP Engine TCPIP Engine is a hardwired logic based network protocol which contains technology of WIZnet ...

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... protocol which supports data communication at the UDP layer. User datagram such as unicast, multicast, and broadcast are supported TCP(Transmission Control Protocol) - This protocol operates in the TCP layer and provides data communication. Both TCP server and client modes are supported. © Copyright 2011 WIZnet Co., Inc. All rights reserved. 15 Ver. 1.12 ...

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... P0.6/AD6 89 P0.7/AD7 90 P2.0/A8 91 GND 92 iMCU W7100A P2.1/A9 93 P2.2/A10 94 P2.3/A11 95 P2.4/A12 96 P2.5/A13 97 P2.6/A14 98 P2.7/A15 99 VCC3V3 100 © Copyright 2011 WIZnet Co., Inc. All rights reserved. Figure 1.7 W7100A Pin Layout 50 LINKLED TXLED 49 RXLED 48 47 COLLED 46 FDXLED SPDLED 45 VCC1V8 44 43 P3.7/A23 42 P3.6/A22 P3.5/A21 41 P3.4/A20 40 39 P3.3/A19 38 ...

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... Package type: QFN 64 Figure 1.8 W7100A QFN 64 Pin Layout 1.4.2 Pin Description The pin functionalities are described in the following table. There are no tri-state output pins and internal signals. Type Description I Input O Output with 8mA driving current IO Input/Output (Bidirectional) Pu Internal pulled-up with 4.7KΩ resistor Pd Internal pulled-down with 85KΩ ...

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... TM3-0 1,2, 2,3, 3,4 4,5 PM2 - 0 70, - 71, 72 BOOTEN 5 6 PLOCK 77 - © Copyright 2011 WIZnet Co., Inc. All rights reserved. I/O Pu/P Description Global asynchronous reset, Active low I Pd Must be connected to GND; value ‘0000’ PHY Mode PM Description Normal Operation Mode Auto-negotiation enabled with all ...

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... Pin number 100pin 64pin nINT0 22 17 nINT1 23 - nINT2 24 - nINT3 25 - XTLN0 61 40 XTLP0 62 41 © Copyright 2011 WIZnet Co., Inc. All rights reserved. I/O Pu/Pd Description I - Timer0 external clock input I - Timer1 external clock input I - Timer0 gate control I - Timer1 gate control I - Timer2 external clock input I - Timer2 Capture/Reload trigger ...

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... © Copyright 2011 WIZnet Co., Inc. All rights reserved. resonant 25MHz crystal or ceramic is connected. If use oscillator, this pin connected with 1.8V output of OSC Crystal output for MCU core, A parallel-resonant 11.0592MHz crystal or ceramic is connected. If oscillator is uesd, this pin can be floated Crystal input for MCU core, A parallel-resonant 11 ...

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... For the best performance, 1. Make the length of RXIP / RXIN signal pair (RX) same if possible. 2. Make the length of TXOP / TXON signal pair (TX) same if possible. 3. Locate the RXIP and RXIN signal as near as possible. © Copyright 2011 WIZnet Co., Inc. All rights reserved Port2 input/output, Ext Memory Addr15 ...

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... Pin number name 100pin 64pin VCC3A3 58, 75 37, 49 VCC3V3 21, 16, 58 38, 73, 87, 100 VCC1A8 54, 34, 42 © Copyright 2011 WIZnet Co., Inc. All rights reserved. I/O Pu/Pd Description O - Link speed LED Low: 100Mbps High: 10Mbps O - Full duplex LED Low: Full-duplex High: Half-duplex O - Collision LED Low: Collision detected (only half-duplex) ...

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... VCC1V8, separated to 1uH inductor and connected to VCC1A8. <Notice> 1V8O is the power supply for W7100A use only. This supply should not be connected with any other devices. 23 Ver. 1.12 ...

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... For more detailed information about the PHYCONF SFR, please refer to the section 2.5.10 ‘New & Extended SFR’. © Copyright 2011 WIZnet Co., Inc. All rights reserved. Figure 1.9 Power Design 64 pin GPIO3[0:7], GPIO2[3:7] ...

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... MODE2 ~ 0 value is 0 (normal mode); Auto configuration mode PHYCONF |= 0x20; // Set the PHY_RSTn bit (reset bit) Delay(); // Delay for reset timing (refer to the section 10 ‘Reset Timing’) PHYCONF &= ~(0x20); // Clear the PHY_RSTn bit © Copyright 2011 WIZnet Co., Inc. All rights reserved. 25 Ver. 1.12 ...

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... Memory” consists the Boot ROM from 0x0000 to 0x07FF and Code FLASH from 0x0000 to 0xFFFF. After the system is reset, the W7100A always executes the code of Boot ROM at “Code Memory.” According to the BOOTEN pin, the code of Boot ROM executes differently. ...

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... Figure 2.2. Boot Sequence Flowchart The initial state of W7100A has both ‘Boot ROM / APP Entry’ and FLASH as shown in Figure 2.3. But since the addresses of ‘Boot ROM / APP Entry’ and FLASH are overlapped, they use same address at 0x0000 ~ 0x07FF / 0xFFF7 ~ 0xFFFF. The iMCU W7100A respectively maps the ‘ ...

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... Set the BOOTEN pin to ‘0’ and clear the RB bit of WCONF register at the startup code. Then the embedded Code FLASH 64KB memory of the W7100A can be completely used as a code memory. 2.1.1 Code Memory Wait States The wait states are managed by internal WTST(0x92) register. The number of wait states is fixed by the value stored in the WTST register. Please refer to the section 2.5.10 ‘ ...

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... Data FLASH. The Data FLASH can be used for saving user IP, MAC, subnet mask or port number. Also the W7100A can address up to 16M bytes of external Data Memory. The figure below shows the Data Memory map. This memory is accessed by MOVX instructions only. The external memory can be extended by user ...

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... EM[2:0] (External Memory Mode) which spaced WCONF(0xFF) of SFR register. When user sets the EM[2:0] to “001”, the port0 is used as address/data bus and the port2 is used as upper side address (A[15:8]). The port1 and port3 is used as GPIO shown the figure below. P0[7:0] W7100A WCONF (0xFF) P1[7:0] EM[2:0]=001 ...

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... The remained port3 can be used as GPIO. Using this method, user can connect data line to address line without latch shown the figure 2.8 as below. W7100A WCONF (0xFF) EM[2:0]=101 Figure 2.8 Direct 8051 External Pin Access Mode (EM[2:0] = “ ...

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... Extended from standard 8051, described in this section Standard – standard 8051 SFR, described in this section All of the SFR in the left hand side column ending with are bit addressable. © Copyright 2011 WIZnet Co., Inc. All rights reserved. Figure 2.10 Internal Memory Map Figure 2.11 SFR Memory Map 32 Ver ...

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... SFR definition The following section describes SFR of W7100A and its functions. For more detailed information about peripheral SFR, please refer to the section 2.5.11 ‘Peripheral SFR’. 2.5.1 Program Code Memory Write Enable Bit Inside the PCON register, the Program Write Enable (PWE) bit is used to enable/disable Program Write signal activity during MOVX instructions. When the PWE bit is set to logic ‘ ...

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... CODE – Data write to the actual modified program byte The code memory can be written by MOVX instruction with minimal 3 wait states. It allows W7100A core to operate with fast and slow code memory devices. The timing diagrams are shown in the Figure below. Figure 2.13 Waveform for code memory Synchronous Write Cycle with Minimal Wait State s(WTST = ‘ ...

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... DPH0(0x83 Figure 2.20 Data Pointer Register DPTR0 DPH1(0x85 Figure 2.21 Data Pointer 1 Register DPTR1 © Copyright 2011 WIZnet Co., Inc. All rights reserved. DPX0 (0x93 DPX.4 DPX.3 DPX.2 DPX.1 DPX1 (0x95 DPX1.4 DPX1.3 DPX1.2 DPX1.1 ...

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... Figure 2.23 Clock Control Register – STRETCH bits The dedicated data memory read/write signals are activated during MOVX instruction. The purpose of MD[2: adjust the communication speed with I/O devices such as slow RAM, © Copyright 2011 WIZnet Co., Inc. All rights reserved. DPS (0x86 ...

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... Internal ram WTST value means below access time in table 2.3. WTST TCPIPCore, Internal flash WTST value means below access time in table 2.4. Table 2.6 TCPIPCore / Flash WTST Bit Values © Copyright 2011 WIZnet Co., Inc. All rights reserved. Table 2.4 MD[2:0] Bit Values Pulse Width[clock] 8 … 3 Not Used Not Used ...

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... SFR user can control the value from 0 to 65535 EW.7 EW.6 EW.5 Figure 2.26 First Byte of Internal Memory Wait States Register EW.15 EW.14 EW.13 Figure 2.27 Second Byte of Internal Memory Wait States Register © Copyright 2011 WIZnet Co., Inc. All rights reserved. Pulse Width[clock ALECON (0x9F AC.4 AC ...

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... Stack Pointer The W7100A has an 8-bit stack pointer called SP(0x81) and is located in the internal RAM space SP.7 SP.6 SP.5 This pointer is incremented before data is stored in PUSH and CALL executions, and decremented after data is popped in POP, RET, and RETI executions. In other words, the Stack pointers always points to the last valid stack byte. 2.5.10 New & ...

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... PHY_PWDN: 1- Power down mode: turn off the embedded Ethernet PHY to save power consumption 0 – Normal operation mode. MODE_EN : 1 – Configure W7100A operation mode using the MODE2 ~ 0 bit / 0 – d on’t use MODE2 ~ 0 bit. and MODE2 ~ 0 bits to configure the operation mode of W7100A MODE2 ~ 0: Please refer to the section 1.4.2 ‘ ...

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... Figure 2.33 Core clock count register CLKCNT0(0xDE): W7100A core clock count register bit16 ~ 23 Bit23 Bit22 Bit21 Figure 2.34 Core clock count register CLKCNT0(0xDF): W7100A core clock count register bit24 ~ 31 Bit31 Bit30 Bit29 Figure 2.35 Core clock count register 2.5.11 Peripheral Registers P0, P1, P2 Port register. For detail information, please refer to the section 4 ‘ ...

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... PSW(0xD0) : Program Status Word Register. For detail information, please refer to the section 1.3.1 ‘ALU’. WDCON(0xD8) : Watchdog Control Register. For detail information, please refer to the section 7 ‘Watchdog Timer’. © Copyright 2011 WIZnet Co., Inc. All rights reserved. refer to the section 5.2 ‘Timer 2’ for the Functionality of Timer 2. 42 ...

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... TCPIPCore Falling (nINT5) The W7100A core is implemented with two levels of interrupt priority control. Each external interrupt can be in high or low level priority group by setting or clearing a bit in the IP(0xB8) and EIP(0xF8) registers. External interrupt pins are activated by a falling edge signal. Interrupt requests are sampled at the rising edge of the system’s clock. ...

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... TR1 TF0 Figure 3.3 Timer0, 1 Configuration Register Note: IT0 - INT0 level (at 0)/edge (at 1) sensitivity IT1 - INT1 level (at 0)/edge (at 1) sensitivity IE0 - INT0 interrupt flag is automatically cleared when processor branches to © Copyright 2011 WIZnet Co., Inc. All rights reserved. IE (0xA8 ...

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... PINT3 - INT3 priority level control (high level at 1) PINT4 – Must be set to ‘0’, if use the EIP register PINT5 - TCPIPCore Interrupt priority level control (high level at 1) PWDI - WATCHDOG priority level control (high level at 1) © Copyright 2011 WIZnet Co., Inc. All rights reserved. SCON (0x98 ...

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... By using softwa re to enable the WDIF, a Watchdog interrupt is generated. Enable d software-set WDIF will generate a Watchdog interrupt. Timed Ac cess Register procedure can be used to modify this bit. © Copyright 2011 WIZnet Co., Inc. All rights reserved. EIF (0x91 ...

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... P1 (0x90), P2 (0xA0), and P3 (0xB0). Some port-reading instructions read from the data registers while others read from the port pin. The “Read-Modify-Write” instructions are directed to the data registers as shown below. © Copyright 2011 WIZnet Co., Inc. All rights reserved. Table 4.1 I/O Ports Pin Description Pu/Pd ...

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... SETB Px.y All other instructions read from a port exclusively through the port pins. All ports pin can be used as GPIO (General Purpose Input Output). The GPIO of W7100A is shown in the Figure below. The output driving voltage of GPIO 3.3V according to the Px_PD/PU SFR value. P0_PD(0xE3): GPIO0 Pull-down register, the value ‘1’ pull-down the related pin. ...

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... Port2[7] Port2[6] Port2[5] P3_PU(0xEE): GPIO3 Pull-up register, the value ‘1’ means pull-up the related pin Port3[7] Port3[6] Port3[5] © Copyright 2011 WIZnet Co., Inc. All rights reserved. P3_PD (0xE6 Port3[4] Port3[3] Port3[2] Figure 4.8 Port3 Pull-down register P0_PU (0xEB ...

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... Timers The W7100A contains two 16-bit timers/counters, Timer0 and Timer 1. In the ‘timer mode’, the timer registers are incremented by every 12 CLK periods. In “counter mode”, the timer registers are incremented during the falling transition on their corresponding input pins T1. The input pins are sampled at every CLK period. ...

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... IP register ET2 Figure 5.3 Interrupt Enable Register Note Enable global interrupts ET0 - Enable Timer0 interrupts ET1- Enable Timer1 interrupts © Copyright 2011 WIZnet Co., Inc. All rights reserved. TMOD (0x89) Timer0 GATE CT M1 ...

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... GATE0 can control Timer0 to manage the pulse width measurements. The 13- bit register consists of 8 bits TH0 and 5 bits of TL0. The upper 3 bits of TL0 should be ignored. Refer to the following Figure for details. © Copyright 2011 WIZnet Co., Inc. All rights reserved. IP (0xB8) 4 ...

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... Mode2 configures the timer register as a 8-bit counter TL0 with automatic reload as shown in the Figure below. During an overflow from TL0, it sets TF0 and reloads the contents of TH0 into TL0. TH0 remains unchanged after the reload is completed. © Copyright 2011 WIZnet Co., Inc. All rights reserved. 53 Ver. 1.12 ...

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... When Timer0 is in Mode3, Timer 1 can be turned on/off by switching itself into Mode3, or can still be used by the serial channel as a baud rate generator any application where interrupt from Timer 1 is not required. Figure 5.9 Timer/Counter0, Mode3: Two 8-Bit Timers/Counters © Copyright 2011 WIZnet Co., Inc. All rights reserved. 54 Ver. 1.12 ...

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... Figure for detail. Figure 5.10 Timer/Counter1, Mode0: 13-Bit Timer/Counter 5.1.8 Timer1 – Mode1 Mode1 is the same as Mode0, except that the timer register is running with all 16 bits. Mode1 is shown in the Figure below. Figure 5.11 Timer/Counter1, Mode1: 16-Bit Timers/Counters © Copyright 2011 WIZnet Co., Inc. All rights reserved. 55 Ver. 1.12 ...

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... Figure 5.12 Timer/Counter1, Mode2: 8-Bit Timer/Counter with Auto-Reload 5.1.10 Timer1 – Mode3 Timer1 in Mode3 holds counting. The effect is the same as setting TR1 = 0 because it is used for Timer0-Mode3. For more detail, please refer to the section 5.1.6 ‘Timer0-Mode3’. © Copyright 2011 WIZnet Co., Inc. All rights reserved. 56 Ver. 1.12 ...

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... T2EX/FA2 Falling I Timer2 of W7100A is fully compatible with the standard 8051 Timer2. A total of five SFR are used to control Timer2 operation, TH2/TL2 (0xCD/0xCC) counter registers, RLDH/RLDL (0xCB/0xCA) capture registers, and T2CON (0xC8) control register. Timer2 works under three modes selected by T2CON bits as shown in the table below. ...

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... The interrupt bits for Timer2 are shown below. An interrupt can be toggled by the IE register, and priorities can be configured by the IP register ET2 Figure 5.15 Interrupt Enable Register — Timer2 © Copyright 2011 WIZnet Co., Inc. All rights reserved. IE (0xA8 ET1 EX1 ...

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... RCLK or TCLK is set. Figure 5.18 Timer/Counter2, 16-Bit Timer/Counter with Capture Mode All of the bits that generate interrupts can be set or cleared by software, with the same result by hardware. That is, interrupts can be generated or cancelled by software. © Copyright 2011 WIZnet Co., Inc. All rights reserved. IP (0xB8 ...

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... Interrupt is generated at the falling edge of T2EX pin with EXEN2 bit enabled. Using the 0x2B vector, EXF2 is set by this interrupt, but the TF2 flag remains unchanged. Figure 5.19 Timer2 for Baud Rate Generator Mode © Copyright 2011 WIZnet Co., Inc. All rights reserved. Table 5.6 Timer2 Interrupt Active ...

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... UART The UART of W7100A operates in full duplex mode which is capable of receiving and transmitting at the same time. Since the W7100A is double-buffered, the receiver is capable of receiving data while the first byte of the buffer is not read. During a read operation, the SBUF reads from the receive register. On the other hand, SBUF loads the data into the transmit register during a send operation ...

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... Bits 2-0 must be written as 0 6.1 Interrupts UART interrupt related bits are shown below. An interrupt can be toggled by the IE register, and priorities can be configured by the IP register. © Copyright 2011 WIZnet Co., Inc. All rights reserved. th transmitted data bit in Modes 2 and 3. This bit is enabled th bit of data received. In Mode1 Table 6 ...

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... Mode0, Synchronous TXD output is a shift clock. The baud rate is fixed at 1/12 of the CLK clock frequency. Eight bits are transmitted with LSB first. Reception is initialized by setting the flags in SCON as follows and REN = 1. © Copyright 2011 WIZnet Co., Inc. All rights reserved. IE (0xA8 ...

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... UART interface. During a transmission, the TB08 bit in th SCON is outputted as the 9 SCON. Figure 6.9 Timing Diagram for UART Transmission Mode2 © Copyright 2011 WIZnet Co., Inc. All rights reserved. bit. While receiving data, the 9 th bit changes the RB08 bit in Ver. 1.12 ...

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... Note: Baud Rate calculation formula Using Timer1 – Baud Rate = ( 2 Using Timer2 – Baud Rate = Clock Frequency / ( 65536 – ( RLDH, RLDL ) ) ) © Copyright 2011 WIZnet Co., Inc. All rights reserved. Timer 1 / Mode2 TH1(0x8D) SMOD = ‘1’ 64(0x40) 160(0xA0) 208(0xD0) ...

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... EA - ET2 Figure 7.2 Interrupt Enable Register Figure 7.3 Extended Interrupt Enable Register Note Enable global interrupt EWDI - Enable Watchdog interrupt © Copyright 2011 WIZnet Co., Inc. All rights reserved. IE (0xA8 ET1 EX1 ET0 EIE (0xE8 EWDI EINT5 EINT4 ...

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... RWT after sets the RWT by software. When a reset occurs, the WTRF (Watchdog Timer reset Flag = WDCON.2) will automatically set to indicate the cause of the reset; however, software must clear this bit manually. © Copyright 2011 WIZnet Co., Inc. All rights reserved. EIP (0xF8) 4 ...

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... System Monitor If the EWT bit of WDCON was set, W7100A will reset when a Watchdog timeout occurs. User can use the Watchdog timer as a system monitor using this function. For example, assuming that an unexpected code was running, there is no RWT clear routine because this code is not designed by user ...

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... Watchdog Timer reset will occur in 512 clock periods (CLK pin) if RWT is not strobed Watchdog interrupt has occurred. Watchdog Timer reset will occur in 512 clock periods (CLK pin) if RWT is not set using Timed Access procedure. © Copyright 2011 WIZnet Co., Inc. All rights reserved. WDCON (0xD8 WDIF ...

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... Clock control register CKCON(0x8E) contains WD[1:0] bits to select Watchdog Timer timeout period. The Watchdog is clocked directly from the CLK pin. The Watchdog has four timeout selections based on the input CLK clock frequency as shown in the Figure 7.1. The selections are a pre-selected number of clocks. *W7100A clock frequency = 88.4736MHz WD[1: ...

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... Common Registers Address offset Symbol 0xFE0000 MR 0xFE0001 GAR0 0xFE0002 GAR1 0xFE0003 GAR2 0xFE0004 GAR3 0xFE0005 SUBR0 0xFE0006 SUBR1 © Copyright 2011 WIZnet Co., Inc. All rights reserved. Figure 8.1 TCPIPCore Memory Map Description Mode Register GAR (Gateway Address Register) SUBR (Subnet Mask Register) 71 Ver. 1.12 ...

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... Interrupt Mask Register RTR (Retransmission Timeout-value Register) RCR (Retransmission Retry-count Register) Reserved PART (PPPoE Authentication Register) PPPoE Authentication Algorithm Register W7100A Version Register Reserved PPP Link Control Protocol Request Timer Register PPP LCP Magic Number Register Reserved INTLEVEL (Interrupt Low Level Timer Register) 72 Ver ...

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... S0_PROTO 0xFE4015 S0_TOS 0xFE4016 S0_TTL 0xFE4017 ~ 0xFE401D © Copyright 2011 WIZnet Co., Inc. All rights reserved. Reserved SOCKET Interrupt Register Description SOCKET 0 Mode Register SOCKET 0 Command Register SOCKET 0 Interrupt Register SOCKET 0 SOCKET Status Register S0_PORT (SOCKET 0 Source Port Register) S0_DHAR (SOCKET 0 Destination Hardware Address Register) ...

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... S1_DHAR4 0xFE410B S1_DHAR5 0xFE410C S1_DIPR0 0xFE410D S1_DIPR1 © Copyright 2011 WIZnet Co., Inc. All rights reserved. SOCKET 0 Receive Memory Size Register SOCKET 0 Transmit Memory Size Register S0_TX_FSR (SOCKET 0 Transmit Free Memory Size Register) S0_TX_RD0 (SOCKET 0 Transmit Memory Read Pointer Register) S0_TX_WR (SOCKET 0 Transmit Memory Write Pointer Register) ...

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... S2_MR 0xFE4201 S2_CR 0xFE4202 S2_IR © Copyright 2011 WIZnet Co., Inc. All rights reserved. S1_DPORT (SOCKET 1 Destination Port Register) S1_MSSR (SOCKET 1 Maximum Segment Size Register) SOCKET 1 Protocol of IP Header Field Register in IP raw mode SOCKET 1 IP Type of Service(TOS) Register SOCKET 1 IP Time to Live(TTL) Register ...

Page 76

... S2_TX_WR1 0xFE4226 S2_RX_RSR0 0xFE4227 S2_RX_RSR1 © Copyright 2011 WIZnet Co., Inc. All rights reserved. SOCKET 2 SOCKET Status Register S2_PORT (SOCKET 2 Source Port Register) S2_DHAR (SOCKET 2 Destination Hardware Address Register) S2_DIPR (SOCKET 2 Destination IP Address Register) S2_DPORT (SOCKET 2 Destination Port Register) S2_MSSR (SOCKET 2 Maximum Segment Size Register) ...

Page 77

... S3_MSSR0 0xFE4313 S3_MSSR1 0xFE4314 S3_PROTO 0xFE4315 S3_TOS © Copyright 2011 WIZnet Co., Inc. All rights reserved. S2_RX_RD (SOCKET 2 Receive Memory Read Pointer Register) S2_RX_WR (SOCKET 2 Receive Memory Write Pointer Register) SOCKET 2 Interrupt Mask Register SOCKET 2 Fragment Field Value in IP Header Register Reserved ...

Page 78

... S4_DHAR1 0xFE4408 S4_DHAR2 0xFE4409 S4_DHAR3 0xFE440A S4_DHAR4 © Copyright 2011 WIZnet Co., Inc. All rights reserved. SOCKET 3 IP Time to Live(TTL) Register Reserved SOCKET 3 Receive Memory Size Register SOCKET 3 Transmit Memory Size Register S3_TX_FSR (SOCKET 3 Transmit Free Memory Size Register) S3_TX_RD (SOCKET 3 Transmit Memory Read Pointer Register) ...

Page 79

... S4_IMR 0xFE442D S4_FRAG0 0xFE442E S4_FRAG1 © Copyright 2011 WIZnet Co., Inc. All rights reserved. S4_DIPR (SOCKET 4 Destination IP Address Register) S4_DPORT (SOCKET 4 Destination Port Register) S4_MSSR (SOCKET 4 Maximum Segment Size Register) SOCKET 4 Protocol of IP Header Field Register in IP raw mode SOCKET 4 IP Type of Service(TOS) Register ...

Page 80

... S5_RXMEM_SIZE 0xFE451F S5_TXMEM_SIZE 0xFE4520 S5_TX_FSR0 0xFE4521 S5_TX_FSR1 © Copyright 2011 WIZnet Co., Inc. All rights reserved. Reserved SOCKET 5 Mode Register SOCKET 5 Command Register SOCKET 5 Interrupt Register SOCKET 5 SOCKET Status Register S5_PORT (SOCKET 5 Source Port Register) S5_DHAR (SOCKET 5 Destination Hardware Address Register) ...

Page 81

... S6_DIPR1 0xFE460E S6_DIPR2 0xFE460F S6_DIPR3 0xFE4610 S6_DPORT0 © Copyright 2011 WIZnet Co., Inc. All rights reserved. S5_TX_RD (SOCKET 5 Transmit Memory Read Pointer Register) S5_TX_WR (SOCKET 5 Transmit Memory Write Pointer Register) S5_RX_RSR (SOCKET 5 Received Data Size Register) S5_RX_RD (SOCKET 5 Receive Memory Read Pointer Register) ...

Page 82

... S7_MR 0xFE4701 S7_CR © Copyright 2011 WIZnet Co., Inc. All rights reserved. S6_MSSR (SOCKET 6 Maximum Segment Size Register) SOCKET 6 Protocol of IP Header Field Register in IP raw mode SOCKET 6 IP Type of Service(TOS) Register SOCKET 6 IP Time to Live(TTL) Register Reserved SOCKET 6 Receive Memory Size Register ...

Page 83

... S7_TX_WR1 0xFE4726 S7_RX_RSR0 0xFE4727 S7_RX_RSR1 © Copyright 2011 WIZnet Co., Inc. All rights reserved. SOCKET 7 Interrupt Register SOCKET 7 SOCKET Status Register S7_PORT (SOCKET 7 Source Port Register) S7_DHAR (SOCKET 7 Destination Hardware Address Register) S7_DIPR (SOCKET 7 Destination IP Address Register) S7_DPORT (SOCKET 7 Destination Port Register) ...

Page 84

... Reserved Reserved 1 Reserved Reserved 0 Reserved Reserved © Copyright 2011 WIZnet Co., Inc. All rights reserved. S7_RX_RD (SOCKET 7 Receive Memory Read Pointer Register) S7_RX_WR (SOCKET 7 Receive Memory Write Pointer Register) SOCKET 7 Interrupt Mask Register S7_FRAG (SOCKET 7 Fragment Field Value in IP Header Register) Reserved ...

Page 85

... Ex) In case of “192.168.0.2” 0xFE000F 192 (0xC0) IR (Interrupt Register) [R] [0xFE0015] [0x00] This register is accessed by the MCU of W7100A to determine the cause of an interrupt. As long as any IR bit is set, the INT5(nINT5: TCPIPcore interrupt) signal is asserted low, and it will not go high until all bits is cleared in the Interrupt Register. 7 ...

Page 86

... This register sets the period of timeout. Value 1 means 100us. The default timeout is 200ms which has a value of 2000 (0x07D0). Ex) For 400ms configuration, set as 4000(0x0FA0) 0xFE0017 0x0F Re-transmission will occur if there is no response or response is delayed from the remote © Copyright 2011 WIZnet Co., Inc. All rights reserved S4_INT S3_INT ...

Page 87

... In TCP communication, the value of Sn_SR is changed to ‘SOCK_CLOSED’ at the same time with Sn_IR(TIMEOUT) = ‘1’. Not in TCP communication, only Sn_IR(TIMEOUT) = ‘1’. The timeout of W7100A can be configurable with RTR and RCR. W7100A’s timeout has ARP and TCP retransmission timeout. At the ARP(Refer to RFC 826, http://www.ietf.org/rfc.html) retransmission timeout, W7100A automatically sends ARP-request to the peer’ ...

Page 88

... X 64000)) X 0.1ms = 318000 X 0.1ms = 31.8s PATR (Authentication Type in PPPoE mode) [R] [0xFE001C-0xFE001D] [0x0000] This register notifies the type of authentication used to establish the PPPoE connection. W7100A supports two types of Authentication method - PAP and CHAP. Value 0xC023 0xC223 PPPALGO (Authentication Algorithm in PPPoE mode)[R][0xFE001E][0x00] This register notifies the authentication algorithm used for the PPPoE connection ...

Page 89

... PLL_CLK) time. IR2 (W7100A SOCKET Interrupt Register)[R/W][0xFE0034][0x00] IR2 is a Register which notifies the host that a W7100A SOCKET interrupt has occurred. When an interrupt occurs, the related bit in IR2 is enabled. In this case, the INT5 (nINT5: TCPIPcore interrupt) signal is asserted low until all of the bits of IR2 is ‘0’. Once the IR2 register is cleared out by using the Sn_IR bits, the INT5 signal is asserted high ...

Page 90

... Sn_MR (SOCKET n Mode Register)[R/W][0xFE4000 + 0x100n][0x0000] This register configures the protocol type or option of SOCKET MULTI Bit Symbol Multicasting 7 MULTI 0 : disable Multicasting 1 : enable Multicasting © Copyright 2011 WIZnet Co., Inc. All rights reserved Description Ver. 1.12 ...

Page 91

... Sn_MR_TCP Sn_MR_UDP Sn_MR_IPRAW 1 P1 S0_MR_MACRAW S0_MR_PPPoE S0_MR_MACRAW and S0_MR_PPPoE are valid only in SOCKET S0_MR_PPPoE is temporarily used for PPPoE server connection/Termination. After connection is established, it can be utilized as another protocol. © Copyright 2011 WIZnet Co., Inc. All rights reserved Closed 0 0 ...

Page 92

... Sn_CR (SOCKET n Command Register)[R/W][0xFE4001 + 0x100n][0x00] This is used to set the command for SOCKET n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE. After W7100A identifies the command, the Sn_CR register is automatically cleared to 0x00. Even though Sn_CR is cleared to 0x00, the command is still being processed. ...

Page 93

... ARP process. 0x22 SEND_KEEP Used in TCP mode © Copyright 2011 WIZnet Co., Inc. All rights reserved. When a ARP timeout occurs (Sn_IR(s)=‘1’) because the Destination Hardware Address is not acquired through the ARP process When a SYN/ACK packet is not received and TCP timeout (Sn_IR(3)) is’ ...

Page 94

... PPP Fail Interrupt, when PAP Authentication is failed PNEXT PPP Next Phase Interrupt, when the phase is changed during ADSL 5 connection process 4 SENDOK SEND OK Interrupt, when the SEND command is completed © Copyright 2011 WIZnet Co., Inc. All rights reserved. Description SEND_OK TIMEOUT Description ...

Page 95

... This register provides the status of SOCKET n. SOCKET status are changed when using the Sn_CR register or during packet transmission/reception. The table below describes the different states of SOCKET n Value Symbol 0x00 SOCK_CLOSED © Copyright 2011 WIZnet Co., Inc. All rights reserved SEND_OK TIMEOUT Description ...

Page 96

... SOCK_MACRAW 0x5F SOCK_PPPOE © Copyright 2011 WIZnet Co., Inc. All rights reserved. In this state, the SOCKET n is opened in TCP mode and initialized the first step of TCP connection establishment. Now, the user can use the LISTEN and CONNECT commands. When Sn_MR(P3:P0) is Sn_MR_TCP and the OPEN command is used, the stage changes to SOCK_INIT ...

Page 97

... This status indicate that a connect-request(SYN packet) is received from a "TCP CLIENT". The socket status changes to SOCK_ESTABLISHED when W7100A successfully transmits connect-accept (SYN/ACK packet "TCP CLIENT". If W7100A fails to send and TCP occurs (Sn_IR(TIMEOUT)=‘1’), the status is changed to SOCK_CLOSED. These statues show the process of terminating a connection. ...

Page 98

... It should be set before OPEN command. Ex) In case of SOCKET 0 port = 5000(0x1388), configure as below, © Copyright 2011 WIZnet Co., Inc. All rights reserved. cf> In UDP and IP RAW mode, the Sn_DIPR register compares the previous and current values. ARP is only used if the two values are different. ...

Page 99

... When using PPPoE-process of W7100A, PPPoE server hardware address is not required to be set. However, even if PPPoE-process of W7100A is not used, but implemented by yourself with MACRAW mode, in order to transmit or receive the PPPoE packet, PPPoE server hardware address(acquired by your PPPoE-process), PPPoE server IP address, and PPP session ID should be set, and MR(PPPoE) also should be set as '1' ...

Page 100

... If there is no user setting value, MSSR is changed to default value. At the TCP or UDP mode, if transmitting data is bigger than the MTU, W7100A automatically divides the data into the MTU unit. MTU is known as MSS in the TCP mode. By selecting from the Host-Written-Value and the peer's MSS, MSS is automatically set as the smaller value through the TCP connection process ...

Page 101

... When SOCKET n is opened in IPRAW mode, it transmits and receives the data of the protocol number set in Sn_PROTO. Sn_PROTO can be assigned in the range of 0x00 ~ 0xFF, but W7100A does not support TCP(0x06) and UDP(0x11) protocol number Protocol number is defined in IANA(Internet assigned numbers authority). For the detail, refer to online document ( http://www ...

Page 102

... Sn_TXMEM_SIZE) of each SOCKET should be 16KB. SUM Ex5) SOCKET 0 : 4KB, SOCKET 1 : 1KB 0xFE401F 0x04 Ex6) SOCKET 2 : 2KB, SOCKET 3 : 1KB 0xFE421F 0x02 Ex7) SOCKET 4 : 2KB, SOCKET 5 : 2KB 0xFE441F 0x02 © Copyright 2011 WIZnet Co., Inc. All rights reserved. 0xFE411E 0x02 0xFE431E 0x01 0xFE451E 0x01 0xFE471E 0x01 n Transmit ...

Page 103

... When reading this register, the user should read the upper bytes (0xFE4024, 0xFE4124, 0xFE4224, 0xFE4324, 0xFE4424, 0xFE4524, 0xFE4624, 0xFE4724) first and the lower bytes (0xFE4025, 0xFE4125, 0xFE4225, 0xFE4325, 0xFE4425, 0xFE4525, 0xFE4625, 0xFE4725) later to get the correct value. © Copyright 2011 WIZnet Co., Inc. All rights reserved. 0xFE471F 0x02 0xFE4021 ...

Page 104

... But this value itself is not the physical address to write. So, the physical address should be calculated as follows: (Refer to the W7100A Driver code) 1. SOCKET n TX Base Address (SBUFBASEADDRESS(n)) and SOCKETn TX Mask Address (SMASK(n)) are calculated on Sn_TXMEM_SIZE(n) value. Refer to the Pseudo code of the Initialization if detail is needed ...

Page 105

... RECV command of SOCKET n Command Register(Sn_CR) and receives data from the remote peer. When reading this register, the user should read the upper byte(0xFE4026, 0xFE4126, 0xFE4226, 0xFE4326, 0xFE4426, 0xFE4526, 0xFE4626, © Copyright 2011 WIZnet Co., Inc. All rights reserved. 105 Ver. 1.12 ...

Page 106

... But this value itself is not the physical address to read. So, the physical address should be calculated as follows: (Refer to the W7100A Driver code) 1. SOCKET n RX Base Address (RBUFBASEADDRESS(n)) and SOCKET n RX Mask Address (RMASK(n)) are calculated on Sn_RXMEM_SIZE(n) value. 2. The bitwise-AND operation of two values, Sn_RX_RD and RMASK(n) gives the result of the offset address (src_mask), in the RX memory range of the SOCKET ...

Page 107

... Sn_FRAG (SOCKET n Fragment Register)[R/W][(0xFE402D + 0x100n) – (0xFE402E + 0x100n)][0x4000] It sets the Fragment field of the IP header at the IP layer. W7100A does not support the packet fragment at the IP layer. Even though Sn_FRAG is configured, IP data is not fragmented, and not recommended either. It should be configured before performing OPEN command. ...

Page 108

... WTST (0x92) can control the code memory access timing. Both two registers can set their value from But in the W7100A, CKCON can set the value 1~7 and WTST can set the value 4~7 only. The other values of both registers are not used. If the user sets the value to an unused value, the W7100A cannot run properly. Detail information can be found in the section 2.5 ‘ ...

Page 109

... Since the serial communication uses interrupt, user must disable the related interrupts when initializing the serial communication. 3) The baud rate should be set to the value which the user will use. Baud rate value for the © Copyright 2011 WIZnet Co., Inc. All rights reserved. Table 9.1 Timer / Counter Mode M ...

Page 110

... W7100A refers to the section 6.6 ‘Examples of Baud Rate Setting’. The calculation of baud rate for the timer is as below ① Calculation formula of timer1 TH1 = 256 – ((K * 88.4736MHz) / (384 * baud rate ‘1’ at SMOD = ‘0’ ‘2’ at SMOD = ‘1’ ② Calculation formula of timer2 (RCAP2H, RCAP2L) = 65536 – ...

Page 111

... Sn_TXMEM_SIZE(ch) = (uint8 *) 2; gS0_TX_MASK = 2K – 1; Same method, set gS1_TX_BASE, gS1_TX_MASK, gS2_TX_BASE, gS2_TX_MASK, gS3_TX_BASE, gS3_TX_MASK, gS4_TX_BASE, gS4_TX_MASK, gS5_TX_BASE, gS5_TX_MASK, gS6_TX_BASE, gS6_tx_MASK, gS7_TX_BASE, gS7_TX_MASK. } © Copyright 2011 WIZnet Co., Inc. All rights reserved. max // Assign 2K rx memory per SOCKET // Assign 2K rx memory per SOCKET = 16KB 16KB) ...

Page 112

... Figure 9.1 Allocation Internal TX/RX memory of SOCKET n If the W7100A initialization process is finished, the W7100A can perform data communication through Ethernet. From this point, the W7100A can transmit the ping-reply of the request packet which is received from network. © Copyright 2011 WIZnet Co., Inc. All rights reserved. ...

Page 113

... Data Communication After the W7100A initialization process, open the SOCKET to TCP or UDP or IPRAW or MACRAW mode. W7100A can transmit and receive the data with others by ‘open’ the SOCKET. The W7100A supports the independently and simultaneously usable 8 SOCKETS. In this section, the communication method for each mode will be introduced. ...

Page 114

... SOCKET initialization is required for TCP data communication. The initialization is opening the SOCKET. The SOCKET opening process selects one SOCKET from 8 SOCKETS of the W7100A, and sets the protocol mode (Sn_MR(P3:P0)) and Sn_PORT0 which is source port number (Listen port number in “TCP SERVER”) in the selected SOCKET, and then executes OPEN command. ...

Page 115

... SOCK_ESTABLISHED) goto ESTABLISHED stage; }  ESTABLISHMENT : Check received data Confirm the reception of the TCP data. First method : { if (Sn_IR(RECV) == ‘1’) Sn_IR(RECV) = ‘1’; goto Receiving Process stage; © Copyright 2011 WIZnet Co., Inc. All rights reserved. // sets source port number // sets OPEN command 115 Ver. 1.12 ...

Page 116

... In this process, it processes the TCP data which was received in the Internal RX memory. At the TCP mode, the W7100A cannot receive the data if the size of received data is larger than the RX memory free size of SOCKET n. If the prior stated condition is happened, the W7100A holds on to the connection (pauses), and waits until the RX memory’ ...

Page 117

... At the send process, user must pad ‘0xFE’ to top-level address of TCPIPCore internal memory as in the receive process first, get the free TX memory size */ FREESIZE: freesize = Sn_TX_FSR; if (freesize < len) goto FREESIZE; /* calculate offset address */ © Copyright 2011 WIZnet Co., Inc. All rights reserved. // len is send size 117 Ver. 1.12 ...

Page 118

... Sn_IR(DISCON)=‘1’; goto CLOSED stage this case, if the interrupt of SOCKET n is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR Second method : { if (Sn_SR == SOCK_CLOSE_WAIT) goto CLOSED stage; } © Copyright 2011 WIZnet Co., Inc. All rights reserved. // dst_mask is offset address // dst_ptr is physical start address Ver. 1.12 118 ...

Page 119

... Sn_IR(TIMEOUT)=‘1’; goto CLOSED stage this case, if the interrupt of SOCKET n is activated, interrupt occurs. Refer to IR, IMR Sn_IMR and Sn_IR Second method : { if (Sn_SR == SOCK_CLOSED) goto CLOSED stage; } © Copyright 2011 WIZnet Co., Inc. All rights reserved 119 Ver. 1.12 ...

Page 120

... It can be used to close the SOCKET n, which disconnected by disconnect-process, or closed by TCP or closed by host’s need without disconnect-process. TO {/* clear the remained interrupts of SOCKET n*/ Sn_IR = 0x00FF; IR(n) = ‘1’; /* set CLOSE command */ Sn_CR = CLOSE; } © Copyright 2011 WIZnet Co., Inc. All rights reserved. 120 Ver. 1.12 ...

Page 121

... TCP when make the “connection SOCKET” with “TCP SERVER” Sn_DIPR = server_ip; Sn_DPORT = server_port; Sn_CR = CONNECT; } © Copyright 2011 WIZnet Co., Inc. All rights reserved. /* set TCP SERVER IP address*/ /* set TCP SERVER listen port number*/ /* set CONNECT command */ 121 Ver. 1.12 ...

Page 122

... The broadcast communication can simultaneously transmit data to destination A, B and C at one time by using “255.255.255.255” IP address. At this time, there is no need to get the © Copyright 2011 WIZnet Co., Inc. All rights reserved. Figure 9.5 UDP Operation Flow can also occur when the user gets TO ...

Page 123

... For the UDP data communication, SOCKET initialization is needed opening the SOCKET. The SOCKET open process is as follows. At first choose the one SOCKET among the 8 SOCKETS of W7100A, then set the protocol mode(Sn_MR(P3:P0)) of the chosen SOCKET and set the source port number Sn_PORT0 for communication. Finally execute the OPEN command. After the OPEN command, the state of Sn_SR is changed to SOCK_UDP ...

Page 124

... SOCKET RX memory */ if ( (src_mask + header_size) > (gSn_RX_MASK + 1) ) {/* copy upper_size bytes of src_ptr to header_addr */ upper_size = (gSn_RX_MASK + 1) – src_mask; wizmemcpy((0xFE0000 + src_ptr), (0x000000 + header_addr), upper_size); /* update header_addr*/ © Copyright 2011 WIZnet Co., Inc. All rights reserved. // src_mask is offset address // src_ptr is physical start address Ver. 1.12 124 ...

Page 125

... Sn_RX_RD as length of len + header_size */ Sn_RX_RD = Sn_RX_RD + get_size + header_size; /* set RECV command */ Sn_CR = RECV; © Copyright 2011 WIZnet Co., Inc. All rights reserved. 125 Ver. 1.12 ...

Page 126

... Sn_TX_WR as length of len */ Sn_TX_WR += len; /* set SEND command */ Sn_CR = SEND; } © Copyright 2011 WIZnet Co., Inc. All rights reserved. // len is send size // dst_mask is offset address // dst_ptr is physical start address 126 Ver. 1.12 ...

Page 127

... Suppose that A, B and C are registered at specified multicast-group. If user transmits data to multicast-group (contains A), the B and C also receive the DATA for A. To use multicast communication, the destination list registers to multicast-group by using IGMP © Copyright 2011 WIZnet Co., Inc. All rights reserved. can occur when user transmits UDP data ...

Page 128

... After the SOCKET opens, the “Report” message is periodically and internally transmitted when the user communicates. The W7100A support IGMP version 1 and version 2 only. If user wants use an updated version, the host processes IGMP directly by using the IPRAW mode SOCKET. SOCKET Initialization  ...

Page 129

... Copyright 2011 WIZnet Co., Inc. All rights reserved. // len is send size // dst_mask is offset address // dst_ptr is physical start address 129 Ver. 1.12 ...

Page 130

... The IPRAW is data communication using TCP, UDP and IP layers which are the lower protocol layers. The IPRAW supports IP layer protocol such as ICMP (0x01) and IGMP (0x02) according to the protocol number. The ‘ping’ of ICMP or IGMP v1/v2 is already included in W7100A by hardware logic. But if the user needs, the host can directly process the IPRAW by opening the SOCKET n to IPRAW ...

Page 131

... Check received data  Refer to the section 9.2.2.1 ‘Unicast & Broadcast’.  Receiving process Process the IPRAW data which is received in internal RX memory. The structure of received IPRAW data is as below. © Copyright 2011 WIZnet Co., Inc. All rights reserved. Figure 9.7 IPRAW Operation Flow 131 Ver. 1.12 ...

Page 132

... SOCKET1~7 in the ‘Hardwired TCP/IP stack’, but it can also be used as a NIC (Network Interface Controller). Therefore, any SOCKET1~7 can be used with ‘Software TCP/IP stack’. Since the W7100A supports ‘Hardwired TCP/IP stack’ and ‘Software TCP/IP stack’, it calls ‘Hybrid TCP/IP stack’. If user wants more SOCKETs beyond the supported 8 SOCKETS, the SOCKET in which the user wants high performance should be utilizing the ‘ ...

Page 133

... OPEN command */ S0_CR = OPEN; /* wait until Sn_SR is changed to SOCK_MACRAW */ if (S0_SR != SOCK_MACRAW) S0_CR = CLOSE; goto START; } Check received data  Refer to the section 9.2.2.1 ‘Unicast & Broadcast’. © Copyright 2011 WIZnet Co., Inc. All rights reserved. Figure 9.9 MACRAW Operation Flow 133 Ver. 1.12 ...

Page 134

... Sn_RX_RD as length of len */ © Copyright 2011 WIZnet Co., Inc. All rights reserved. below src_mask is offset address // src_ptr is physical start address // Read the 2bytes PACKET-INFO 134 ...

Page 135

... RX memory */ if((S0_RXMEM_SIZE(0) * 1024) – S0_RX_RSR(0) < 1528) { received_size = S0_RX_RSR(0); S0_CR = CLOSE; while(S0_SR != SOCK_CLOSED); © Copyright 2011 WIZnet Co., Inc. All rights reserved. /* backup Sn_RX_RSR */ /* SOCKET Closed */ /* wait until SOCKET is closed */ closes to full. 135 ...

Page 136

... Sn_SR is changed to SOCK_MACRAW */ while (S0_SR != SOCK_MACRAW); } else /* process normally the DATA packet from internal RX memory */ {/* This block is same as the code of “Receiving process” stage*/ © Copyright 2011 WIZnet Co., Inc. All rights reserved. // src_mask is offset address // src_ptr is physical start address Ver. 1.12 136 ...

Page 137

... Sn_TX_WR as length of len */ S0_TX_WR += send_size; /* set SEND command */ S0_CR = SEND; } © Copyright 2011 WIZnet Co., Inc. All rights reserved. // dst_mask is offset address // dst_ptr is physical start address Ver. 1.12 137 ...

Page 138

... SEND command completion */ while(S0_IR(SENDOK)==‘0’); S0_IR(SENDOK) = ‘1’; } Check finished / SOCKET close  Refer to the section 9.2.2.1 ‘Unicast & Broadcast’. © Copyright 2011 WIZnet Co., Inc. All rights reserved. /* wait interrupt of SEND completion */ /* clear previous interrupt of SEND completion */ 138 Ver. 1.12 ...

Page 139

... Power consumption(Driving voltage 3.3V) Symbol Parameter I Current consumption Boot I Current consumption Idle I Current consumption Active I Current consumption Power-down © Copyright 2011 WIZnet Co., Inc. All rights reserved. Rating -0.5 to 3.6 -0.5 to 5.5 (5V tolerant 3.3 (GPIO) -0.5 to 3.6 (Others)  - -55 to 125 Test Condition Min Typ Junction 3.0 3 ...

Page 140

... Crystal Characteristics Parameter Frequency Frequency Tolerance (at 25℃) Shunt Capacitance Drive Level Load Capacitance Aging (at 25℃) © Copyright 2011 WIZnet Co., Inc. All rights reserved. Description 25 MHz ±30 ppm 7pF Max 1 ~ 500uW (100uW typical) 18pF ±3ppm / year Max Min ...

Page 141

... In the case of using the internal PHY mode, be sure to use symmetric transformer in order to support Auto MDI/MDIX (Crossover). In the case of using the External PHY mode, use the transformer which is suitable for external PHY specification. © Copyright 2011 WIZnet Co., Inc. All rights reserved. Transmit End 1:1 1:1 ...

Page 142

... Time maintained above: – Temperature (TL) – Time (tL) Peak/Classification Temperature (Tp) Time within 5 °C of actual Peak Temperature (tp) RAMp-Down Rate Time 25 °C to Peak Temperature © Copyright 2011 WIZnet Co., Inc. All rights reserved 3° C/second max. 150 °C 200 °C 60-180 seconds 217 °C 60-150 seconds 260 + 0 ° ...

Page 143

... Package Descriptions 12.1 Package type: LQFP 100 © Copyright 2011 WIZnet Co., Inc. All rights reserved. 143 Ver. 1.12 ...

Page 144

... A is defined as the distance from the seating plane to the lowest point of the 1 package body. ⑦ Controlling dimension : Millimeter ⑧ Reference Document : JEDEC MS-026 , BED. © Copyright 2011 WIZnet Co., Inc. All rights reserved. MILLIMETER NOM. MAX. MIN. - 1.60 ...

Page 145

... Package type: QFN 64 * CONTROLLING DIMENSION: mm © Copyright 2011 WIZnet Co., Inc. All rights reserved. 145 Ver. 1.12 ...

Page 146

... Exact shape and size of this feature is optional. ⑥ Package WARPAGE max 0.08mm. ⑦ Applied for exposed pad and terminals, exclude embedding part of exposed pad from measuring. ⑧ Applied to terminals. © Copyright 2011 WIZnet Co., Inc. All rights reserved. MILLIMETER NOM. MAX. MIN. ...

Page 147

... Summary The 8-bit operation cycles of the 80C51 and W7100A with addition, subtraction, multiplication and division are as below briefly shows its performance. The W7100A with ‘wizmemcpy’ (supported by WIZnet) function is almost 9 times faster than the 80C51. 80C51 cycle ADD ...

Page 148

... Cycle ISP / wizmemcpy Byte 80C51 Cycle ISP / wizmemcpy W7100A Cycle FLASH / user code W7100A Cycle FLASH / user code W7100A Cycle FLASH / user code 148 Ver. 1.12 ...

Page 149

... Cycle ISP / wizmemcpy Byte 80C51 Cycle ISP / wizmemcpy W7100A Cycle FLASH / user code W7100A Cycle FLASH / user code W7100A Cycle FLASH / user code 149 Ver. 1.12 ...

Page 150

... Byte 80C51 Cycle ISP / wizmemcpy W7100A Cycle FLASH / user code W7100A Cycle FLASH / user code W7100A Cycle FLASH / user code 150 Ver. 1.12 ...

Page 151

... Byte 80C51 Cycle ISP / wizmemcpy W7100A Cycle FLASH / user code W7100A Cycle FLASH / user code W7100A Cycle FLASH / user code 4 151 Ver. 1.12 ...

Page 152

... ISP / wizmemcpy 144 W7100A Cycle FLASH / user code 152 Ver. 1.12 ...

Page 153

... Byte 80C51 Cycle ISP / wizmemcpy W7100A Cycle FLASH / user code W7100A Cycle FLASH / user code 153 Ver. 1.12 ...

Page 154

... MUL AB A4h MOV R6, A F8h – FFh MOV R1, B A8h – AFh MOV A, R3 E8h – EFh MOV B, R7 88h – 8Fh MUL AB A4h © Copyright 2011 WIZnet Co., Inc. All rights reserved ...

Page 155

... C8h – CFh ADDC A, B 38h – 3Fh MOV R5, A F8h – FFh CLR A E4h ADDC A, R4 38h – 3Fh MOV R4, A F8h – FFh Sum : © Copyright 2011 WIZnet Co., Inc. All rights reserved ...

Page 156

... Add the INTLEVEL register to TCPIPCore common register Delete about PPPoE protocol cause of errata Add new SFR definition, modify the GPIO in/out voltage, delete the UIPR and UPORT register for W7100A Remove information about external memory accessing Added 64pin number information to “Pin Description” section ...

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