CY62136ESL-45ZSXI Cypress Semiconductor Corp, CY62136ESL-45ZSXI Datasheet - Page 7

• Manufacturer Part Number: CY62136ESL-45ZSXI
• Description: IC SRAM 2MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62136ESL-45ZSXI

• Memory Size: 2M (128K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Maximum Clock Frequency: 1 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Organization: 128 K x 16
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.2 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document #: 001-48147 Rev. *C
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0
15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
16. At any temperature and voltage condition, t
17. t
18. The internal write time of the memory is defined by the overlap of WE, CE = V
Parameter
to 3 V, and output loading of the specified I
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
HZOE
, t
HZCE
[14,15]
[18]
, t
HZBE
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to power-up
CE HIGH to ower-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to High Z
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High Z
WE HIGH to Low Z
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
[16]
[16]
OL
HZCE
[16, 17]
[16, 17]
[16]
[16, 17]
/I
OH
is less than t
as shown in the
[16]
[16, 17]
Description
LZCE
, t
AC Test Loads and Waveforms on page 5
HZBE
is less than t
IL
, BHE, BLE or both = V
LZBE
, t
HZOE
is less than t
IL
. All signals must be active to initiate a write and any of these
LZOE
Min
application note AN13842
45
10
10
45
35
35
35
35
25
10
–
–
–
5
–
–
0
–
–
5
–
0
0
0
–
, and t
CY62136ESL MoBL
45 ns
HZWE
is less than t
Max
45
45
22
18
18
45
22
18
18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
for further clarification
LZWE
Page 7 of 15
for any device
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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