MT47H32M8BP-37E:B TR Micron Technology Inc, MT47H32M8BP-37E:B TR Datasheet - Page 5
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MT47H32M8BP-37E:B TR
Manufacturer Part Number
MT47H32M8BP-37E:B TR
Description
IC DDR2 SDRAM 256MBIT 60FBGA
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H16M16BG-3B_TR.pdf
(128 pages)
Specifications of MT47H32M8BP-37E:B TR
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
256M (32M x 8)
Speed
3.75ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-FBGA
Organization
32Mx8
Density
256Mb
Address Bus
15b
Access Time (max)
500ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
160mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1049-2
List of Tables
Table 1: Key Timing Parameters ...................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions .......................................................................... 15
Table 4: Input Capacitance ............................................................................................................................ 19
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 20
Table 6: Temperature Limits .......................................................................................................................... 21
Table 7: Thermal Impedance ......................................................................................................................... 22
Table 8: General I
Table 9: I
Table 10: DDR2 I
Table 11: AC Operating Specifications and Conditions .................................................................................... 26
Table 12: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 37
Table 13: ODT DC Electrical Characteristics ................................................................................................... 38
Table 14: Input DC Logic Levels ..................................................................................................................... 39
Table 15: Input AC Logic Levels ..................................................................................................................... 39
Table 16: Differential Input Logic Levels ........................................................................................................ 40
Table 17: Differential AC Output Parameters .................................................................................................. 42
Table 18: Output DC Current Drive ................................................................................................................ 42
Table 19: Output Characteristics .................................................................................................................... 43
Table 20: Full Strength Pull-Down Current (mA) ............................................................................................ 44
Table 21: Full Strength Pull-Up Current (mA) ................................................................................................. 45
Table 22: Reduced Strength Pull-Down Current (mA) ..................................................................................... 46
Table 23: Reduced Strength Pull-Up Current (mA) .......................................................................................... 47
Table 24: Input Clamp Characteristics ........................................................................................................... 48
Table 25: Address and Control Balls ............................................................................................................... 49
Table 26: Clock, Data, Strobe, and Mask Balls ................................................................................................. 49
Table 27: AC Input Test Conditions ................................................................................................................ 50
Table 28: DDR2-400/533 Setup and Hold Time Derating Values (
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values (
Table 30: DDR2-400/533
Table 31: DDR2-667/800/1066
Table 32: Single-Ended DQS Slew Rate Derating Values Using
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 36: Truth Table – DDR2 Commands ..................................................................................................... 64
Table 37: Truth Table – Current State Bank n – Command to Bank n ............................................................... 65
Table 38: Truth Table – Current State Bank n – Command to Bank m .............................................................. 67
Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 68
Table 40: Burst Definition .............................................................................................................................. 72
Table 41: READ Using Concurrent Auto Precharge ......................................................................................... 93
Table 42: WRITE Using Concurrent Auto Precharge ........................................................................................ 99
Table 43: Truth Table – CKE ......................................................................................................................... 114
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
DD7
Timing Patterns (4-Bank Interleave READ Operation) ................................................................ 23
DD
DD
Specifications and Conditions ......................................................................................... 24
Parameters .................................................................................................................... 23
t
DS,
t
DH Derating Values with Differential Strobe ..................................................... 56
t
DS,
t
DH Derating Values with Differential Strobe ............................................ 57
5
t
DS
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
IS and
b
and
REF
REF
REF
256Mb: x4, x8, x16 DDR2 SDRAM
t
) at DDR2-667 ..................................... 58
) at DDR2-533 ..................................... 59
) at DDR2-400 ..................................... 59
IS and
t
t
DH
IH) ................................................... 52
b
.................................................. 58
t
IH) .......................................... 53
©2003 Micron Technology, Inc. All rights reserved.