ZLF645E0Q2032G Maxim Integrated, ZLF645E0Q2032G Datasheet - Page 138
ZLF645E0Q2032G
Manufacturer Part Number
ZLF645E0Q2032G
Description
8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
Manufacturer
Maxim Integrated
Datasheet
1.ZLF645E0H4864G2204.pdf
(201 pages)
Specifications of ZLF645E0Q2032G
Core
Z8
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Program Memory Size
32 KB
Data Ram Size
1 KB
On-chip Adc
No
Operating Supply Voltage
2 V to 3.6 V
Package / Case
QFN-EP-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Number Of Programmable I/os
5
Number Of Timers
2 x 8 bit, 1 x 16 bit
On-chip Dac
No
Processor Series
ZLF645
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2 V
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Table 63. Interrupt Priority Register (IPR)
19-4572; Rev 0; 4/09
Bit
Field
Reset
R/W
Address
Bit Position
[7:6]
[5]
Interrupt Priority Register
Reserved
X
7
Programming bits for the Interrupt Edge Select are located in the IRQ register (R250),
bit 6 and bit 7.
Table 62. Interrupt Request Register
The Interrupt Priority register (see
priority. Interrupts are divided into three groups of two—Group A, Group B, and Group C.
IPR bits 4, 3, and 0 determine which interrupt group has priority. For example, if interrupts
IRQ5, IRQ1, and IRQ0 occur simultaneously when IPR[4:3,0]=001b, the interrupts are
serviced in the following order: IRQ1, IRQ0, IRQ5.
IPR bits 5, 2, and 1 determine which interrupt within each group has higher priority.
Value
IRQ Bit
7
0
0
1
1
Note: F = Falling Edge; R = Rising Edge.
—
0
1
—
X
6
Description
Reserved
Reads are undefined; writes must be 00b.
Group A Priority (IRQ3, IRQ5)
IRQ5 > IRQ3
IRQ3 > IRQ5
6
0
1
0
1
Group A
Priority
Table 62
W
X
5
Interrupt Edge
IRQ2 (P31)
F
F
R
R/F
Bank Independent: F9h; Linear: 0F9h
provides the configuration.
Group Priority
X
4
[2:1]
W
Table
IRQ0 (P32)
F
R
F
R/F
X
3
63) defines which interrupt holds the highest
Group B
Priority
W
X
2
ZLF645 Series Flash MCUs
Group C
Priority
W
X
1
Product Specification
Interrupt Priority Register
Group Priority
[0]
W
X
0
130
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