C8051F330DR Silicon Labs, C8051F330DR Datasheet - Page 86

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C8051F330DR

Manufacturer Part Number
C8051F330DR
Description
8-bit Microcontrollers - MCU 8kB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F330DR

Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
8 KB
Data Ram Size
768 B
On-chip Adc
No
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
QFN-20
Mounting Style
SMD/SMT
Data Rom Size
128 B
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
4
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
1500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
9.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
EA
Bit7
EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-
tings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
ESPI0
R/W
Bit6
SFR Definition 9.7. IE: Interrupt Enable
ET2
R/W
Bit5
ES0
R/W
Bit4
Rev. 1.7
ET1
R/W
Bit3
EX1
R/W
Bit2
C8051F330/1/2/3/4/5
ET0
R/W
Bit1
(bit addressable)
EX0
R/W
Bit0
SFR Address:
00000000
Reset Value
0xA8
89

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