C8051F330DR Silicon Labs, C8051F330DR Datasheet - Page 96

• Manufacturer Part Number: C8051F330DR
• Description: 8-bit Microcontrollers - MCU 8kB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F330DR

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: QFN-20
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

Important Note: The V
V
dure for configuring the V
See Figure 10.2 for V
See Table 10.1 for complete electrical characteristics of the V
10.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete RST pin
specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
10.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
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Bit7:
Bit6:
Bits5–0: Reserved. Read = 000000b. Write = don’t care.
VDMEN
monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce-
R/W
Bit7
Step 1. Enable the V
Step 2. Wait for the V
Step 3. Select the V
VDMEN: V
This bit turns the V
until it is also selected as a reset source in register RSTSRC (SFR Definition 10.2). The V
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
V
See Table 10.1 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
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VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
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DD
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monitor as a reset source before it has stabilized may generate a system reset.
STAT: V
Bit6
R
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
SFR Definition 10.1. VDM0CN: V
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monitor timing; note that the reset delay is not incurred after a V
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Monitor Enable.
monitor must be enabled before it is selected as a reset source. Selecting the
Status.
monitor as a reset source is shown below:
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Bit5
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R
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monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
monitor (VDMEN bit in VDM0CN = ‘1’).
monitor to stabilize (see Table 10.1 for the V
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monitor circuit on/off. The V
monitor threshold.
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Bit4
R
monitor threshold.
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Rev. 1.7
Monitor turn-on time.
Bit3
R
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C8051F330/1/2/3/4/5
Bit2
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R
monitor.
Monitor cannot generate system resets
Monitor Control
Monitor output).
Bit1
R
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Monitor turn-on time).
SFR Address:
Bit0
R
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monitor reset.
0xFF
Reset Value
Variable
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99