C8051F314R Silicon Labs, C8051F314R Datasheet - Page 181
Manufacturer Part Number
8-bit Microcontrollers - MCU 8KB 10ADC
Specifications of C8051F314R
8-bit Microcontrollers - MCU
Data Bus Width
Maximum Clock Frequency
Program Memory Size
Data Ram Size
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
A/d Bit Size
A/d Channels Available
Data Rom Size
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
Number Of Timers
Program Memory Type
Factory Pack Quantity
Supply Voltage - Max
Supply Voltage - Min
Bits 3–2: NSSMD1–NSSMD0: Slave Select Mode.
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to
the SPI0 data register was attempted while a data transfer was in progress. It must be
cleared by software.
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode
collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not auto-
matically cleared by hardware. It must be cleared by software.
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buf-
fer still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
Selects between the following NSS operation modes:
Slave Mode Operation” on page
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
assume the value of NSSMD0.
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1,
indicating that it is safe to write a new byte to the transmit buffer.
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
Section “16.2. SPI0 Master Mode Operation” on page 175
SFR Definition 16.2. SPI0CN: SPI0 Control
RXOVRN NSSMD1 NSSMD0
SFR Address: 0xF8
Section “16.3. SPI0