AT45DB021D-SH-T Atmel, AT45DB021D-SH-T Datasheet
AT45DB021D-SH-T
Specifications of AT45DB021D-SH-T
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AT45DB021D-SH-T Summary of contents
Page 1
... RapidS serial interface is SPI compatible for fre- quencies up to 66MHz. Its 2-,162-,688-bits of memory are organized as 1,024-pages of 256-bytes or 264-bytes each. In addition to the main memory, the AT45DB021D also contains one SRAM buffer of 256-/264-bytes. EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three step read-modify-write opera- tion ...
Page 2
... The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB021D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). ...
Page 3
... The metal pad on the bottom of the UDFN package is floating. This pad can be a “No Connect” or connected to GND Figure 1-3. Block Diagram WP PAGE (256-/264-BYTES) BUFFER (256-/264-BYTES) SCK CS RESET VCC GND 3638J–DFLASH–5/10 Figure 1- GND 6 VCC 5 WP FLASH MEMORY ARRAY I/O INTERFACE SI Atmel AT45DB021D (1) UDFN Top View SCK GND 2 7 RESET VCC ...
Page 4
... Main memory addressing is referenced using the terminology A17 - A0, where A17 - A8 denotes the 10- address bits required to designate a page address and denotes the eight address bits required to designate a byte address within a page. Atmel AT45DB021D 4 ® AT45DB021D is divided into three levels of BLOCK ARCHITECTURE BLOCK 0 SECTOR 0a BLOCK 1 BLOCK 2 ...
Page 5
... As with crossing over page 3638J–DFLASH–5/10 ™ protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit perform a continuous read array with the CAR1 Atmel AT45DB021D specification. The CAR1 5 ...
Page 6
... Command allows data to be sequentially read directly from the buffer. Two opcodes, D4H or D1H, can be used for the Buffer Read Command. The use of each opcode depends on the maximum SCK frequency that will be used to Atmel AT45DB021D perform a continuous read array with the page size set to CAR2 specification ...
Page 7
... DataFlash standard buffer (264-bytes), the opcode must be clocked into . During this time, the status register will indicate that the part is busy During this time, the status register will indicate that the part is busy. P Atmel AT45DB021D CAR2 . 7 ...
Page 8
... PA7) and 16 don’t care bits. To perform sector 0a or sector 0b erase for Atmel AT45DB021D 8 . During this time, the status register will indicate that the part is busy. ...
Page 9
... During this time, the Status Register will indicate that the device is busy. CE Byte 1 Byte 2 C7H 94H Opcode Opcode Opcode Byte 2 Byte 3 Byte 4 Atmel AT45DB021D PA3/ PA2/ PA1/ PA0/ A11 A10 • • • • • • • • • ...
Page 10
... Table 6-1. Enable Sector Protection Command Command Enable Sector Protection Figure 6-1. Enable Sector Protection CS Opcode SI Byte 1 Each transition represents 8 bits Atmel AT45DB021D 10 . During this time, the status register will indicate that the part EP Byte 1 Byte 2 3DH 2AH Opcode Opcode Opcode Byte 2 ...
Page 11
... A noise filter is incorporated to help protect against spurious noise that may inadvertently assert or deassert the WP pin. 3638J–DFLASH–5/10 Byte 1 Byte 2 3DH 2AH Opcode Opcode Opcode Byte 2 Byte 3 Byte 4 CC Atmel AT45DB021D Byte 3 Byte 4 7FH 9AH , then the content of the Sector Protection Register time. When the WP pin is WPE time) as WPD 11 ...
Page 12
... Sectors 0a, 0b Unprotected Protect Sector 0a Protect Sector 0b (Page 8-127) Protect Sectors 0a (Page 0-7), 0b (Page 8-127) Note: 1. The default value for bytes 0 through 7 when shipped from Atmel is 00H x = don’t care Atmel AT45DB021D 12 2 Enable Sector Protection Disable Sector Command Protection Command – ...
Page 13
... Byte 1 Byte 2 3DH 2AH Opcode Opcode Opcode Byte 2 Byte 3 Byte 4 Atmel AT45DB021D , during which time the PE Byte 3 Byte 4 7FH CFH Section 7.1, the Sector , during which P 13 ...
Page 14
... Table 7-6. Read Sector Protection Register Command Command Read Sector Protection Register Note Dummy Byte Figure 7-4. Read Sector Protection Register CS SI Opcode SO Each transition represents 8 bits Atmel AT45DB021D 14 Byte 1 Byte 2 3DH 2AH Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Byte 1 ...
Page 15
... Figure 8-1. Sector Lockdown CS Opcode SI Byte 1 Each transition represents 8 bits 3638J–DFLASH–5/10 Byte 1 Byte 2 3DH 2AH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes Atmel AT45DB021D , during which time the Status Register will P Byte 3 Byte 4 7FH 30H Address Address Bytes Bytes 15 ...
Page 16
... Sector Lockdown Register. Table 8-4. Sector Lockdown Register Command Read Sector Lockdown Register Note Dummy Byte Figure 8-2. Read Sector Lockdown Register CS SI Opcode SO Each transition represents 8 bits Atmel AT45DB021D 16 0 (0a, 0b) See Below 0a (Page 0-7) Bit Byte 1 Byte 2 35H xxH ...
Page 17
... Security Register Byte Number 1 · · · One-time User Programmable Opcode Opcode Opcode Byte 2 Byte 3 Byte 4 Atmel AT45DB021D 64 65 · · · 126 127 Factory Programmed By Atmel , during which time the P Data Byte Data Byte Data Byte ® ...
Page 18
... Auto Page Rewrite This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion within a sector. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Atmel AT45DB021D ...
Page 19
... If bit zero is a zero, then the page size is set to 264-bytes. The device density is indicated using bits five, four, three, and two of the status register. For Atmel AT45DB021D, the four bits are 0101 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
Page 20
... After resuming form Deep Power-down, the device RDPD will return to the normal standby mode. Table 10-2. Resume from Deep Power-down Command Resume from Deep Power-down Figure 10-2. Resume from Deep Power-Down CS SI Opcode Each transition represents 8 bits Atmel AT45DB021D 20 Bit 5 Bit 4 Bit 3 Bit Bit 1 Bit 0 PROTECT ...
Page 21
... SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by 3638J–DFLASH–5/10 Section 21. “Ordering Information” on page 11.1). , during which time the Status Register will indicate that the device is busy. The P Byte 1 Byte 2 3DH 2AH Opcode Opcode Byte 3 Byte 4 Atmel AT45DB021D ® ® DataFlash standard 43. Byte 3 Byte 4 80H A6H 21 ...
Page 22
... A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manu- facturers), the Manufacturer ID data is comprised of only one byte. Atmel AT45DB021D 22 JEDEC Assigned Code ...
Page 23
... Group C can be executed. During the internally self-timed portion of Group B commands five through ten, only Group C commands three and four can be executed. Finally, during the internally self-timed portion of a Group D command, only the Status Register Read command should be executed. 3638J–DFLASH–5/10 Atmel AT45DB021D 23 ...
Page 24
... Command Enable Sector Protection Disable Sector Protection Erase Sector Protection Register Program Sector Protection Register Read Sector Protection Register Sector Lockdown Read Sector Lockdown Register Program Security Register Read Security Register Atmel AT45DB021D 24 Opcode D2H E8H 03H 0BH D1H D4H Opcode ...
Page 25
... Table 13-5. Legacy Commands Command Buffer Read Main Memory Page Read Continuous Array Read Status Register Read Note: 1. These legacy commands are not recommended for new designs 3638J–DFLASH–5/10 (1) Atmel AT45DB021D Opcode 53H 60H 58H B9H ABH D7H 9FH Opcode 54H ...
Page 26
... Page Size = 256-bytes Opco de Opcode 03h 0Bh 50h 53h 58h 60h 77h 7Ch 81h 82h 83h 84h 88h 9Fh B9h ABh D1h D2h D4h D7h E8h Note Don’t Care Atmel AT45DB021D 26 Address Byte Address Byte N/A N Address Byte ...
Page 27
... P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t Care 3638J–DFLASH–5/10 Address Byte Address Byte N/A 1 N Atmel AT45DB021D Address Byte N/A N/A N/A N/A N/A N N/A N Additional Don’t Care Bytes N/A N N/A N N/A N/A N/A N ...
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... In an effort to continue our goal of maintaining world-class quality leadership, Atmel has been performing extensive testing on the Atmel AT45DB021D that would not normally be done with a Serial Flash device. The testing that has been performed on the AT45DB021D involved extensive, non-stop reading of the memory array on pre- conditioned devices ...
Page 29
... Voltage Extremes referenced in the "Absolute Maximum Ratings" are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time Atmel AT45DB021D -40°C to 85°C 2.7V to 3.6V 29 ...
Page 30
... IH V Output Low Voltage OL V Output High Voltage OH Notes during a buffer read is 20mA maximum @ 20MHz CC1 2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design tolerant Atmel AT45DB021D 30 Condition Min CS, RESET all IH inputs at CMOS levels CS, RESET all IH inputs at CMOS levels f = 20MHz 0mA ...
Page 31
... RESET Pulse Width RST t RESET Recovery Time REC Figure 16-1. Input Test Waveforms and Measurement Levels 2.4V AC DRIVING LEVELS 0.45V < 2ns (10 3638J–DFLASH–5/10 AC 1.5V MEASUREMENT LEVEL Atmel AT45DB021D Min Typ Max Units 66 MHz 66 MHz 33 MHz 6.8 ns 6.8 ns 0.1 V/ns 0.1 V/ ...
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... VALID IN Figure 17-2. Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66MHz CSS WL SCK t V HIGH Z SO VALID OUT t SU VALID IN SI Atmel AT45DB021D 32 page 32. Waveform 1 shows the SCK signal being low when CS ® RapidS CSH DIS HIGH IMPEDANCE VALID OUT ...
Page 33
... SCK. 3638J–DFLASH–5/10 = 66MHz) MAX CSH DIS VALID OUT 66MHz) MAX CSH VALID OUT t H ® ™ RapidS function's ability to operate at higher clock frequencies, a full clock cycle Atmel AT45DB021D CS HIGH IMPEDANCE t CS DIS HIGH IMPEDANCE ® is designed to always 33 ...
Page 34
... Note: The CS signal should be in the high state before the RESET signal is deasserted Figure 17-7. Command Sequence for Read/Write Operations for Page Size 256-Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) CMD MSB 6 Don’t Care Bits Atmel AT45DB021D ...
Page 35
... PA0) (BA8 - BA0/BFA8 - BFA0) FLASH MEMORY ARRAY BUFFER TO MAIN MEMORY BUFFER WRITE I/O INTERFACE SI BINARY PAGE SIZE 16 DON'T CARE + BFA7-BFA0 CMD X X···X, BFA8 Atmel AT45DB021D LSB Byte/Buffer Address Completes writing into the buffer n BFA7-0 n+1 Last Byte 35 ...
Page 36
... MAIN MEMORY PAGE TO BUFFER BUFFER (256-/264-BYTES) BUFFER READ Figure 18-1. Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) Atmel AT45DB021D 36 Starts self-timed erase/program operation BINARY PAGE SIZE A17- DON'T CARE BITS CMD PA9-7 PA6-0, X FLASH MEMORY ARRAY MAIN MEMORY PAGE READ ...
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... X···X, PA9-7 BINARY PAGE SIZE 16 DON'T CARE + BFA7-BFA0 CMD X X..X, BFA8 Each transition represents 8 bits ADDRESS BITS MSB Atmel AT45DB021D Starts reading page data into buffer BINARY PAGE SIZE XXXX XXXX PA6- Dummy Byte BFA7 DON'T CARE BITS MSB DATA BYTE ...
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... Figure 19-2. Continuous Array Read (Opcode 0BH SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 19-3. Continuous Array Read (Low Frequency: Opcode 03H SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 19-4. Main Memory Page Read (Opcode: D2H SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT45DB021D ADDRESS BITS A17 - MSB ADDRESS BITS A17- MSB ...
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... STANDARD ATMEL DATAFLASH PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 MSB ADDRESS BITS BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0 STANDARD ATMEL DATAFLASH PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 MSB DON'T CARE MSB Atmel AT45DB021D DON'T CARE MSB DATA BYTE MSB DATA BYTE MSB MSB DATA BYTE ...
Page 40
... Figure 19-8. Read Sector Lockdown Register (Opcode 35H SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 19-9. Read Security Register (Opcode 77H SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 19-10. Status Register Read (Opcode D7H SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT45DB021D DON'T CARE MSB DON'T CARE MSB ...
Page 41
... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array 3638J–DFLASH–5/ 1FH DEVICE ID BYTE 1 DEVICE ID BYTE 2 shown for SI and SO represents one byte (8 bits) START provide address and data BUFFER TO MAIN MEMORY PAGE PROGRAM END Atmel AT45DB021D 00H BUFFER WRITE (84H) (83H) 41 ...
Page 42
... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details Atmel AT45DB021D 42 START ...
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... AT45DB021D-MH-SL954 (4) AT45DB021D-MH-SL955 AT45DB021D-SSH-B AT45DB021D-SSH-T AT45DB021D-SSH-SL954 AT45DB021D-SSH-SL955 AT45DB021D-SH-B AT45DB021D-SH-T (3) AT45DB021D-SH-SL954 (4) AT45DB021D-SH-SL955 Notes: 1. The shipping carrier option is not marked on the devices 2. Standard parts are shipped with the page size set to 264-bytes. The user is able to configure these parts to a 256- byte page size if desired 3 ...
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... K 8 Pin #1 Notch (Option Bottom View L Notes: 1. This package conforms to JEDEC reference MO-229, Saw Singulation. 2. The terminal # Laser-marked Feature. Package Drawing Contact: packagedrawings@atmel.com Atmel AT45DB021D Option A 1 (0. TITLE 8MA1, 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) ...
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... Package Drawing Contact: packagedrawings@atmel.com 3638J–DFLASH–5/ TITLE 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) Atmel AT45DB021D Ø Ø END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM MAX A 1.35 – ...
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... Mismatch of the upper and lower dies and resin burrs are not included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com Atmel AT45DB021D Top View ...
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... Changed part number ordering code to reflect NiPdAu lead finish - Changed AT45DB021D-MU to AT45DB021D-MH - Changed AT45DB021D-SSU to AT45DB021D-SSH - Changed AT45DB021D-SU to AT45DB021D-SH Added lead finish details to Ordering Information table Added Ordering Code Detail Fixed the typographical error, under Status Register Read, to indicate that bit “0” ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...