EVAL-AD5259DBZ Analog Devices, EVAL-AD5259DBZ Datasheet

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EVAL-AD5259DBZ

Manufacturer Part Number
EVAL-AD5259DBZ
Description
Digital Potentiometer Development Tools EVALUATION BOARD I.C.
Manufacturer
Analog Devices
Series
AD5259r
Datasheet

Specifications of EVAL-AD5259DBZ

Rohs
yes
Product
Evaluation Boards
Tool Is For Evaluation Of
AD5259
Resistance
5 kOhms/10 kOhms/50 kOhms/100 kOhms
Operating Supply Voltage
5 V
Description/function
Nonvolatile, I2C compatible 256-position, digital potentiometer
Interface Type
I2C
Maximum Operating Temperature
+ 85 C
Factory Pack Quantity
1
For Use With
Sim DAC Web Tool
Data Sheet
FEATURES
Nonvolatile memory maintains wiper settings
256-position
Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package
Compact MSOP-10 (3 mm × 4.9 mm × 1.1mm) package
I
V
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time < 1ms
Software write protect command
Address Decode Pin AD0 and Pin AD1 allow
100-year typical data retention at 55°C
Wide operating temperature −40°C to +125°C
3 V to 5 V single supply
APPLICATIONS
LCD panel V
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
Electronics level settings
GENERAL DESCRIPTION
The AD5259 provides a compact, nonvolatile LFCSP-10
(3 mm × 3 mm) or MSOP-10 (3 mm × 4.9 mm) packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function
as mechanical potentiometers
with enhanced resolution and solid-state reliability.
The wiper settings are controllable through an I
digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM, providing an end-to-end tolerance accuracy of 0.1%.
A separate V
users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to four devices on the same bus.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2
C®-compatible interface
LOGIC
4 packages per bus
pin provides increased interface flexibility
COM
LOGIC
adjustment
pin delivers increased interface flexibility. For
1
or variable resistors, but
Document Feedback
2
C-compatible
256-Position, Digital Potentiometer
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
V
1
GND
SCL
SDA
AD0
AD1
LOGIC
The terms digital potentiometer, VR (variable resistor), and RDAC are used
interchangeably.
GND
SDA
SCL
AD0
AD1
V
DD
INTERFACE
Nonvolatile, I
SERIAL
V
INTERFACE
LOGIC
ON RESET
I
2
POWER-
SERIAL
C
I
2
Figure 2. Block Diagram Showing Level Shifters
C
FUNCTIONAL BLOCK DIAGRAMS
DECODE LOGIC
DECODE LOGIC
COMMAND
CONTROL
SDA
ADDRESS
AD0
AD1
SCL
EEPROM
©2005–2012 Analog Devices, Inc. All rights reserved.
CONNECTION DIAGRAM
LOGIC
W
8
8
Figure 1. Block Diagram
1
2
3
4
5
DATA
CONTROL
(Not to Scale)
EEPROM
Figure 3. Pinout
AD5259
TOP VIEW
CONTROL LOGIC
RDAC
DECODE LOGIC
DECODE LOGIC
REGISTER
COMMAND
SHIFTER
ADDRESS
LEVEL
RDAC
AND
2
10
C-Compatible
9
8
7
6
A
B
V
GND
V
DD
LOGIC
REGISTER
RDAC
V
DD
AD5259
AD5259
www.analog.com
RDAC
A
W
B
A
W
B

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EVAL-AD5259DBZ Summary of contents

Page 1

... Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...

Page 2

... Read Modes ................................................................................. 17 Store/Restore Modes .................................................................. 17 Tolerance Readback Modes ...................................................... 18 ESD Protection of Digital Pins and Resistor Terminals ........ 19 Power-Up Sequence ................................................................... 19 Layout and Power Supply Bypassing ....................................... 19 Multiple Devices on One Bus ................................................... 19 Evaluation Board ........................................................................ 19 Display Applications ...................................................................... 20 Circuitry ...................................................................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 22 7/05—Rev Rev. A Added 10-Lead LFCSP ...................................................... Universal Changes to Features Section and General Description Section ...

Page 3

Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS ± 10 ± 10 LOGIC Table 1. Parameter DC CHARACTERISTICS: RHEOSTAT MODE Resistor Differential Nonlinearity 5 kΩ 10 kΩ 50 kΩ/100 kΩ Resistor Integral ...

Page 4

AD5259 Parameter DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Leakage Current SDA, AD0, AD1 SCL – Logic High SCL – Logic Low Input Capacitance POWER SUPPLIES Power Supply Range Positive Supply Current Logic Supply Logic Supply Current ...

Page 5

Data Sheet TIMING CHARACTERISTICS ± 10 ± 10 LOGIC Table 2. Parameter INTERFACE TIMING 1 CHARACTERISTICS SCL Clock Frequency t Bus Free Time Between Stop BUF ...

Page 6

AD5259 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND DD LOGIC GND MAX 1 Pulsed Continuous Digital Inputs and Output ...

Page 7

Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin Mnemonic ADO 3 AD1 4 SDA 5 SCL 6 V LOGIC 7 GND EPAD W A ...

Page 8

AD5259 TYPICAL PERFORMANCE CHARACTERISTICS 5 kΩ +25°C; unless otherwise noted. DD LOGIC AB A 1.5 1.3 2.7V 1.1 0.9 0.7 0.5 0.3 0.1 –0.1 –0.3 5.5V –0 ...

Page 9

Data Sheet 0.5 0.4 0.3 0.2 0.1 –40°C 0 –0.1 –0.2 –0.3 –0.4 –0 128 160 CODE (Decimal) Figure 12. R-INL vs. Code vs. Temperature 0.5 0.4 0.3 T 0.2 0.1 0 –0 +25°C ...

Page 10

AD5259 400 100kΩ 300 50kΩ 200 10kΩ 100 0 –100 –200 –300 5kΩ –400 –500 –600 128 CODE (Decimal) Figure 18. Rheostat Mode Tempco (Δ 10kΩ 20 100kΩ ...

Page 11

Data Sheet – – – – – – – –48 –54 –60 1k 10k FREQUENCY (Hz) Figure 24. Gain vs. Frequency vs. Code, ...

Page 12

AD5259 1µs/DIV Figure 30. Midscale Glitch, Code 0×7F to 0× SCL 2 Figure 31. Large Signal Settling Time Rev Page Data Sheet W 200ns/DIV ...

Page 13

Data Sheet TEST CIRCUITS Figure 32 through Figure 37 illustrate the test circuits that define the test conditions used in the product Specifications tables DUT 1LSB = V+/ Figure 32. Test Circuit ...

Page 14

AD5259 THEORY OF OPERATION The AD5259 is a 256-position digitally-controlled variable resistor (VR) device. EEPROM is pre-loaded at midscale from the factory, and initial power-up is, accordingly, at midscale. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance (R ) ...

Page 15

Data Sheet I 2 C-COMPATIBLE INTERFACE The master initiates data transfer by establishing a start condi- tion, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 4). The next byte is the ...

Page 16

AD5259 I 2 C-COMPATIBLE FORMAT The following generic, write, read, and store/restore control registers for the AD5259 all refer to the device addresses listed in Table 5; the mode/condition reference key (S, P, SA, MA, NA and ...

Page 17

Data Sheet READ MODES Read modes are referred to as traditional because the first two bytes for all three cases are dummy bytes, which function to place the pointer towards the correct register; this is the reason for the repeat ...

Page 18

AD5259 TOLERANCE READBACK MODES Table 15. Traditional Readback of Tolerance (Individually) 7-Bit Device Address S (See Table Slave Address Byte Instruction Byte 7-Bit Device Address S (See ...

Page 19

... Table 5). This allows up to four devices on the bus to be written to or read from independently. before applying any EVALUATION BOARD An evaluation board, with all necessary software, is available are powered LOGIC to program the AD5259 from any PC running Windows® 98/ 2000/ XP. The graphical user interface, as shown in Figure 45, ...

Page 20

AD5259 DISPLAY APPLICATIONS CIRCUITRY A special feature of the AD5259 is its unique separation of the V and V supply pins. The separation provides greater LOGIC DD flexibility in applications that do not always provide needed supply voltages. In particular, ...

Page 21

Data Sheet OUTLINE DIMENSIONS IDENTIFIER PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 3.10 3.00 2.90 5. 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.15 0.23 ...

Page 22

... AD5259BRMZ50- AD5259BCPZ50- AD5259BRMZ100 100 k AD5259BRMZ100-R7 100 k AD5259BCPZ100-R7 100 k EVAL-AD5259DBZ RoHS Compliant Part. 2 The evaluation board is shipped with the 10 kΩ R Package Description Temperature –40°C to +125°C 10-Lead MSOP –40°C to +125°C 10-Lead MSOP –40°C to +125°C 10-Lead LFCSP_WD – ...

Page 23

Data Sheet NOTES Rev Page AD5259 ...

Page 24

... AD5259 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. D05026-0-10/12(C) Rev Page Data Sheet ...

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