S-24CS01AFJ-TB-G Seiko Instruments, S-24CS01AFJ-TB-G Datasheet - Page 15

IC EEPROM 1KBIT 400KHZ 8SOP

S-24CS01AFJ-TB-G

Manufacturer Part Number
S-24CS01AFJ-TB-G
Description
IC EEPROM 1KBIT 400KHZ 8SOP
Manufacturer
Seiko Instruments
Datasheet

Specifications of S-24CS01AFJ-TB-G

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
1K (128 x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Rev.4.5
6. 3 Write Protection
6. 4 Acknowledge Polling
Write protection is available in the S-24CS01A/02A/04A/08A. When the WP pin is connected to the V
write operation to memory area is forbidden at all.
When the WP pin is connected to the GND, the write protection is invalid, and write operation in all
memory area is available.
Fix the level of the WP pin from the rising edge of SCL for loading the last write data (D0) until the end of
the write time (10 ms max.). If the WP pin changes during this time, the address data being written at this
time is not guaranteed.
There is no need for using write protection, the WP pin should be connected to the GND. The write
protection is valid in the operating voltage range.
Acknowledge polling is used to know the completion of the write cycle in the E
After the E
and no response is made to the signal transmitted by the master device.
Accordingly the master device can recognize the completion of the write cycle in the E
detecting a response from the slave device after transmitting the start condition, the device address and
the read/write instruction code to the E
That is, if the E
E
Keep the level of the WP pin fixed until acknowledge is confirmed.
It is recommended to use the read instruction "1" as the read/write instruction code transmitted by the
master device.
SCL
SDA
WP
2
PROM generates an acknowledge, the write cycle has been completed.
_00
Write Data
2
PROM receives a stop condition and once starts the write cycle, all operations are forbidden
2
PROM does not generate an acknowledge, the write cycle is in progress and if the
D0
Acknowledge
Figure 15 WP Pin Fixed Period
2
Seiko Instruments Inc.
PROM, namely to the slave devices.
WP Pin Fixed Period
Condition
Stop
t
WR
2-WIRE CMOS SERIAL E
S-24CS01A/02A/04A/08A
2
PROM.
Condition
Start
2
PROM by
2
PROM
CC
15
,

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