S-24CS64A0I-J8T1G Seiko Instruments, S-24CS64A0I-J8T1G Datasheet - Page 15

• Manufacturer Part Number: S-24CS64A0I-J8T1G
• Description: IC EEPROM 64KBIT 400KHZ 8SOP
• Manufacturer: Seiko Instruments

Specifications of S-24CS64A0I-J8T1G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev.4.2
7. Read
7.1 Current Address Read
Either in writing or in reading the E
incremented by one. The memory address is maintained as long as the power voltage is higher than the
current address hold voltage V
The master device can read the data at the memory address of the current address pointer without
assigning the word address as a result, when it recognizes the position of the address pointer in the
E
In the following the address counter in the E
When the E
following a start condition, it responds with an acknowledge.
Next an 8-bit data at the address “n” is sent from the E
address counter is incremented at the falling edge of the SCL clock for the 8th bit data, and the content of
the address counter becomes n+1.
The master device outputs stop condition not an acknowledge, the reading of E
Attention should be paid to the following point on the recognition of the address pointer in the E
In the read operation the memory address counter in the E
falling edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand,
the upper 8 bits of the memory address are left unchanged and are not incremented at the falling edge of
the SCL clock for the 8th bit of the received data.
2
PROM. This is called “Current Address Read”.
_00
2
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1”
SDA LINE
S
T
A
R
T
AH
.
M
S
B
1 0 1 0
Figure 15 Current Address Read
ADDRESS
2
DEVICE
Seiko Instruments Inc.
PROM holds the last accessed memory address, internally
A2 A1 A0
2
PROM is assumed to be “n”.
L
S
B
R
W
R
E
A
D
1
/
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
2
2
PROM is automatically incremented at every
PROM synchronous to the SCL clock. The
NO ACK from
Master Device
2-WIRE CMOS SERIAL E
DATA
ADR INC
2
PROM is ended.
S
T
O
P
S-24CS64A
2
PROM.
2
PROM
15