DK-DEV-5AGTD7N Altera Corporation, DK-DEV-5AGTD7N Datasheet
DK-DEV-5AGTD7N
Specifications of DK-DEV-5AGTD7N
Related parts for DK-DEV-5AGTD7N
DK-DEV-5AGTD7N Summary of contents
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Arria V GT FPGA Development Kit User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01124-1.0 Arria V GT FPGA Development Kit User Guide Feedback Subscribe ...
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice ...
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... User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 The Flash Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Random Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 CFI Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Increment Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 November 2012 Altera Corporation Contents Arria V GT FPGA Development Kit User Guide ...
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... Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23 The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24 Power Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25 Power Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25 Graph Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25 Calculating Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25 The Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26 Arria V GT FPGA Development Kit User Guide Contents November 2012 Altera Corporation ...
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... Restoring the Flash Device to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4 Restoring the MAX II CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5 Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 November 2012 Altera Corporation v Arria V GT FPGA Development Kit User Guide ...
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... Arria V GT FPGA Development Kit User Guide Contents November 2012 Altera Corporation ...
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... You can also request to have Altera mail the software to you on DVDs. Quartus II Software Your kit includes a license for the Development Kit Edition (DKE) of the Quartus II software (Windows platform only). For one year, this license entitles you to most of the features of the Subscription Edition (excluding the IP Base Suite). ...
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... After the year, your DKE license will no longer be valid and you will not be permitted to use this version of the Quartus II software. To continue using the Quartus II software, you should download the free Quartus II Web edition or purchase a subscription to Quartus II software. For more information, refer to the Software page of the Altera website ...
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... For information about measuring board and FPGA power in real time, refer to f For more information about power consumption and thermal modeling, refer to AN 358: Thermal Management for November 2012 Altera Corporation Manual. “The Power Monitor” on page 6–23. FPGAs. ...
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... For Arria V GT OrCAD symbols, refer to the For Nios II 32-bit embedded processor solutions, refer to the ■ Processing Arria V GT FPGA Development Kit User Guide page. page. page. Chapter 2: Getting Started References Arria V GT Development Documentation: Arria V Devices page. Capture CIS Symbols page. Embedded November 2012 Altera Corporation ...
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... Purchasing this kit entitles you to a one-year license for the Development Kit Edition (DKE) of the Quartus II software. After the year, your DKE license will no longer be valid and you will not be permitted to use this version of the Quartus II software. To continue using the Quartus II software, you should download the free Quartus II Web edition or purchase a subscription to Quartus II software ...
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... Chapter 3: Software Installation Installing the Quartus II Subscription Edition Software Figure 3–1 shows 3S150SPXXXX as an example serial page to license your product for a specific user (you) Manage Computers and Manage Users Altera Software Installation and Licensing November 2012 Altera Corporation pages allow Manual. ...
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... Contains the original data programmed onto the board before shipment. Use this data to restore factory_recovery the board with its original factory contents. November 2012 Altera Corporation page of the Altera website. Alternatively, you can request Altera Kit Installations DVD Request Form Figure 3– ...
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... Altera website, locate the table entry for your configuration and click the link to access the instructions. f For USB-Blaster II configuration details, refer to the Arria V GT FPGA Development Kit User Guide Chapter 3: Software Installation Installing the USB-Blaster II Driver Altera Programming Cable Driver Information On-Board USB-Blaster II November 2012 Altera Corporation page. ...
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... When configuration is complete, the Config Done LED (D16) illuminates, signaling that the Arria V GT device configured successfully. f For more information about the PFL megafunction, refer to Megafunction User November 2012 Altera Corporation 4. Development Board Setup Guide. to return the board Figure 4–1/Figure 4–2 ...
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... FAN2 (installed) FAN1 J23 SW5 PCIe Width ON SW7 Chapter 4: Development Board Setup Factory Default Switch and Jumper Settings ON J11 (installed) J14 J28 SW6 MSEL SW8 November 2012 Altera Corporation ...
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... Set DIP switch bank (SW5) to match Table 4–2. SW5 Board Settings Dip Switch Switch 1 CLK_SEL 2 CLK_EN 3 Factory1 4 Factory2 November 2012 Altera Corporation Table 4–1 (1) Board Function Label Switch 1 has the following options: When ON, a logic 0 is selected. ■ When OFF, a logic 1 is selected. ■ ...
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... Switch 3 has the following options presence detect is enabled. ■ OFF ( presence detect is disabled. ■ — Chapter 4: Development Board Setup Factory Default Switch and Jumper Settings and Figure 4–2. Default Position OFF and Figure 4–2. Default Position OFF November 2012 Altera Corporation ...
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... Set the board jumpers to match Table 4–6. Jumper Settings (Part Board Reference J5 FMC_VCCPD J11 FMC_VCCIO_SEL J14 FAN2 November 2012 Altera Corporation Table 4–5 (1) Board Function Label Switch 1 has the following options: When ON, a logic 0 is selected. ■ When OFF, a logic 1 is selected. ...
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... V. Do not install an FMC with a higher rated card. Note: FMC is not available for rev. A boards. Powers the fan for FPGA 1. Manual. Chapter 4: Development Board Setup Factory Default Switch and Jumper Settings Default Position Pins 1-2 Installed Arria V GT FPGA November 2012 Altera Corporation ...
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... Attach the Ethernet cable from the board to your LAN. 3. Power up the board. The board connects to the LAN’s gateway router and obtains an IP address. The LCD on the board displays the IP address. November 2012 Altera Corporation 5. Board Update Portal “Restoring the Flash ...
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... Using the Board Update Portal to Update User Designs Arria V GT FPGA Development Kit Arria V GT FPGA Development Kit “Connecting to the Board Update Portal Web Page” “Restoring the Flash Device A–4. Chapter 5: Board Update Portal page to page include for information about to access November 2012 Altera Corporation ...
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... The Board Test System GUI communicates over the JTAG bus to a test design running in the Arria V GT device. factory configuration. Figure 6–1. Board Test System Graphical User Interface November 2012 Altera Corporation 6. Board Test System 3–3. Figure 6–1 shows the initial GUI for a board that is in the ...
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... USB cable is attached and the board is on. Arria V GT FPGA Development Kit User Guide “Factory Default Switch and Jumper Settings” page 4–2. Arria V GT FPGA Development Board Reference Chapter 6: Board Test System Preparing the Board ® II Embedded Logic section Manual. November 2012 Altera Corporation ...
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... To configure the FPGA with a test system design, perform the following steps: 1. Make sure there are no conflicts between the Quartus II software version and the Board Test System GUI version. November 2012 Altera Corporation “The Configure Menu” (Figure 6–2) to select the design you want to use. Each design 6– ...
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... Determines which of the up to eight (0-7) pages of flash Read / Write memory to use for FPGA reconfiguration. The flash memory ships with pages 0 and 1 preconfigured. Chapter 6: Board Test System Using the Board Test System Figure 6–1 on page 6–1 page of the Description November 2012 Altera Corporation ...
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... If you plug in an external USB-Blaster cable to the JTAG header (J1), the On-Board USB-Blaster II is disabled. f For details on the JTAG chain, refer to the Reference Manual. USB-Blaster II November 2012 Altera Corporation Read/Write Capability When set to 0, the value in PSR determines the page of flash memory to use for FPGA reconfiguration. When set to Read / Write 1, the value in PSS determines the page of flash memory to use for FPGA reconfiguration ...
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... If you exceed the 16 character display limit on either line, a warning message appears. Arria V GT FPGA Development Kit User Guide off, and detect push button presses. Chapter 6: Board Test System Using the Board Test System Figure 6–3 shows the November 2012 Altera Corporation ...
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... Press a push button on the board to see the graphical display change accordingly. The Flash Tab The Flash tab Figure 6–4. The Flash Tab November 2012 Altera Corporation (Figure 6–4) allows you to read and write flash memory on your board. 6–7 Arria V GT FPGA Development Kit ...
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... Displays the flash memory map for the Arria V GT FPGA Development Kit. Arria V GT FPGA Development Kit User Guide Figure 6–1 on page 6–1 and Table A–1 on page Chapter 6: Board Test System Using the Board Test System A–1). November 2012 Altera Corporation ...
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... Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected. November 2012 Altera Corporation (Figure 6–5) allows you to perform loopback tests on the transceiver ports. ...
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... HF2—next highest frequency divide-by-4 data pattern 1100110011001100. ■ HF3—second lowest frequency divide-by-8 data pattern 1111000011110000. Arria V GT FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System test. The following November 2012 Altera Corporation ...
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... TX and RX performance bars—Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve. Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per ■ second. November 2012 Altera Corporation 6–11 Arria V GT FPGA Development Kit User Guide ...
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... Channel lock—Shows the channel locked or unlocked state. When locked, all lanes are word aligned and channel bonded. Arria V GT FPGA Development Kit User Guide (Figure 6–6) allows you to run test designs using the Chapter 6: Board Test System Using the Board Test System November 2012 Altera Corporation ...
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... The Data type control specifies the type of data contained in the transactions. The following data types are available for analysis: ■ PRBS7—Selects pseudo-random 7-bit sequences. PRBS15—Selects pseudo-random 15-bit sequences. ■ November 2012 Altera Corporation 6–13 test. The following Arria V GT FPGA Development Kit User Guide ...
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... Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per ■ second. Start The Start control initiates transaction performance analysis. Stop The Stop control terminates transaction performance analysis. Arria V GT FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System November 2012 Altera Corporation ...
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... Pattern sync—Shows the pattern synced or not synced state. The pattern is ■ considered synced when the start of the data sequence is detected. November 2012 Altera Corporation (Figure 6–7) allows you to perform loopback tests on the XCVR 6–15 ...
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... HF2—next highest frequency divide-by-4 data pattern 1100110011001100. ■ ■ HF3—second lowest frequency divide-by-8 data pattern 1111000011110000. ■ LF FMC—lowest frequency divide-by-40 data pattern. Arria V GT FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System test. The following November 2012 Altera Corporation ...
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... Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per second. Start The Start control initiates transaction performance analysis. Stop The Stop control terminates transaction performance analysis. November 2012 Altera Corporation 6–17 Arria V GT FPGA Development Kit User Guide ...
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... Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected. Arria V GT FPGA Development Kit User Guide (Figure 6–8) allows you perform loopback tests on the Bull’s Chapter 6: Board Test System Using the Board Test System November 2012 Altera Corporation ...
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... LF Bull’s Eye—lowest frequency divide-by-32 data pattern. ■ ■ LF SDI—lowest frequency divide-by-10 data pattern. 1 Settings HF1, HF2, HF3, LF are for transmit observation only. November 2012 Altera Corporation 6–19 test. The following Arria V GT FPGA Development Kit User Guide ...
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... Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per ■ second. Start The Start control initiates transaction performance analysis. Stop The Stop control terminates transaction performance analysis. Arria V GT FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System November 2012 Altera Corporation ...
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... Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected. November 2012 Altera Corporation (Figure 6–9) allows you perform loopback tests on the SMA 6–21 port ...
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... HF3—second lowest frequency divide-by-8 data pattern 1111000011110000. ■ LF—lowest frequency divide-by-32 data pattern. ■ 1 Settings HF1, HF2, HF3, LF are for transmit observation only. Arria V GT FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System test. The following November 2012 Altera Corporation ...
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... You can also run the Power Monitor as a stand-alone application. PowerMonitor.exe resides in the <install dir>\kits\arriaVGT_5agtfd7kf40_fpga\examples\board_test_system directory. On Windows, click Start > All Programs > Altera > Arria V GT FPGA Development Kit <version> > Power Monitor to start the application. November 2012 Altera Corporation 6–23 Arria V GT FPGA Development Kit User Guide ...
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... Power Rail—Selects the power rail to measure. After selecting the desired rail, click Reset to refresh the screen with new board readings. Arria V GT FPGA Development Kit User Guide Chapter 6: Board Test System The Power Monitor Figure 6–10 shows the Arria V GT FPGA Development November 2012 Altera Corporation ...
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... The first measurement is Vsense and the difference between the two measurements is Vdif. Plug the values into the equation to determine the power consumption. November 2012 Altera Corporation Arria V GT FPGA Manual. Arria V GT FPGA Development Kit 6– ...
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... MAX II device through a 2-wire serial bus. Figure 6–11. The Clock Control The following sections describe the Clock Control controls. Arria V GT FPGA Development Kit User Guide Chapter 6: Board Test System The Clock Control Manual. Figure 6–11 shows the Clock Control. November 2012 Altera Corporation ...
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... Start the Quartus II Programmer. 2. Click Auto Detect to display the devices in the JTAG chain. 3. Click Add File and select the path to the desired .sof. 4. Turn on the Program/Configure option for the added file. November 2012 Altera Corporation 6–27 Arria V GT FPGA Development Kit User Guide ...
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... Arria V GT FPGA Development Kit User Guide Arria V GT FPGA Development Board Reference page on the Samtec website. Chapter 6: Board Test System Samtec High-speed Bull’s Eye Connector Altera Arria V GX FPGA November 2012 Altera Corporation ...
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... Altera recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with the Altera tools. If you unintentionally overwrite the factory hardware or factory software image, refer to Flash Device to the Factory Settings” on page November 2012 Altera Corporation A. Programming the Flash Memory Size KB Address Range 128 0x07FE ...
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... Appendix A: Programming the Flash Memory Device page of the Altera website or create .flash files from your own page of the Altera website. “Using the Board Update Portal to Update User for more information. Preparing Design Files for Flash Programming Arria V GT FPGA November 2012 Altera Corporation ...
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... Programming the board is now complete. f For more information about the nios2-flash-programmer utility, refer to the Flash Programmer User November 2012 Altera Corporation “Configuring the FPGA Using the Quartus II for more information. “Creating Flash Files Using the Nios II A–2) and type the following Nios II EDS command: Guide. A– ...
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... MAC address. Arria V GT FPGA Development Kit User Guide Appendix A: Programming the Flash Memory Device Restoring the Flash Device to the Factory Settings 4–2. “Configuring the FPGA Using the Quartus II for more information. November 2012 Altera Corporation “Factory Default ...
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... To ensure that you have the most up-to-date factory restore files and information about this product, refer to the website. November 2012 Altera Corporation Guide. To ensure that you have the most up-to-date factory page of the Altera website. 4–2. Arria V GT FPGA Development Kit A– ...
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... A–6 Arria V GT FPGA Development Kit User Guide Appendix A: Programming the Flash Memory Device Restoring the MAX II CPLD to the Factory Settings November 2012 Altera Corporation ...
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... The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters italic type Initial Capital Letters November 2012 Altera Corporation Changes (1) Contact Method Website Website Email Website ...
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... Altera documents. The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document. Additional Information Typographic Conventions page of the Altera November 2012 Altera Corporation ...