MT48LC8M8A2P-75:G Micron Technology Inc, MT48LC8M8A2P-75:G Datasheet - Page 16

• Manufacturer Part Number: MT48LC8M8A2P-75:G
• Description: IC SDRAM 64MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M8A2P-75:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (8M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 8Mx8
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5:
CAS Latency
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Burst Definition
Notes:
1. For full-page accesses: y = 1,024 (x4); y = 512 (x8); y = 256 (x16).
2. For BL = 2, A1–A9 (x4), A1–A8 (x8), or A1–A7 (x16) select the block-of-two burst; A0 selects
3. For BL = 4, A2–A9 (x4), A2–A8 (x8), or A2–A7 (x16) select the block-of-four burst; A0–A1
4. For BL = 8, A3–A9 (x4), A3–A8 (x8), or A3–A7 (x16) select the block-of-eight burst; A0–A2
5. For a full-page burst, the full row is selected and
6. A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) select the starting column.
7. Whenever a boundary of the block is reached within a given sequence above, the following
8. For BL = 1, A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) select the unique column to be accessed,
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n and the latency is m clocks, the data will
be available by clock edge n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a read command is registered at T0 and the
latency is programmed to two clocks, the DQs will start driving after T1 and the data will
be valid by T2, as shown in Figure 7 on page 17. Table 6 on page 17 indicates the oper-
ating frequencies at which each CL setting can be used.
Full page (y)
the starting column within the block.
select the starting column within the block.
select the starting column within the block.
access wraps within the block.
and mode register bit M3 is ignored.
Length
Burst
2
4
8
Starting Column Address
A2
0
0
0
0
1
1
1
1
n = A0–A9/8/7
(location 0–y)
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
16
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Type = Sequential
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
…Cn - 1, Cn…
Order of Accesses Within a Burst
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
64Mb: x4, x8, x16 SDRAM
Functional Description
©2000 Micron Technology, Inc. All rights reserved.
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0