MT48LC2M32B2P-55:G Micron Technology Inc, MT48LC2M32B2P-55:G Datasheet - Page 19

• Manufacturer Part Number: MT48LC2M32B2P-55:G
• Description: IC SDRAM 64MBIT 5.5NS 86TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC2M32B2P-55:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 5.5ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operations
Bank/Row Activation
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
REFRESH command except CKE is disabled (LOW). When the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for
required for the completion of any internal refresh in progress.
Upon exiting self refresh mode, AUTO REFRESH commands must be issued every
15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Self refresh is not supported on automotive temperature devices.
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated. See Figure 6 on page 20.
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
issued. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 7 on page 20, which covers
any case where 2 <
specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
t
RCD (MIN)/
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
19
t
t
CK - 3 (the same procedure is used to convert other
RCD specification.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RAS and may remain in self refresh mode
t
RCD (MIN) should be divided by
t
XSR because time is
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Commands
t
RC.