MT48LC2M32B2P-5:G Micron Technology Inc, MT48LC2M32B2P-5:G Datasheet - Page 36

• Manufacturer Part Number: MT48LC2M32B2P-5:G
• Description: IC SDRAM 64MBIT 200MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC2M32B2P-5:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOP
• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 4.5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 280mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 4.5 ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Concurrent Auto Precharge
READ with Auto Precharge
WRITE with Auto Precharge
Figure 27:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Internal
States
READ with Auto Precharge Interrupted by a READ
COMMAND
Note:
ADDRESS
BANK m
BANK n
CLK
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
DQ
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 27).
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 28 on page 37).
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 29 on page 37).
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 30 on page 38).
DQM is LOW.
Page Active
T0
NOP
t
WR is met, where
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
READ with Burst of 4
CL = 3 (BANK n)
T2
NOP
t
WR begins when the WRITE to bank m is registered. The last
36
BANK m,
READ - AP
T3
BANK m
COL d
Interrupt Burst, Precharge
READ with Burst of 4
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WR is met, where
T4
CL = 3 (BANK m)
NOP
D
OUT
a
t
RP - BANK n
T5
NOP
D
a + 1
OUT
t
WR begins when the READ to
T6
NOP
D
OUT
©2001 Micron Technology, Inc. All rights reserved.
d
64Mb: x32 SDRAM
DON’T CARE
Idle
T7
NOP
t RP - BANK m
Precharge
D
d + 1
OUT
Commands