MT48LC2M32B2P-5:G Micron Technology Inc, MT48LC2M32B2P-5:G Datasheet - Page 41

• Manufacturer Part Number: MT48LC2M32B2P-5:G
• Description: IC SDRAM 64MBIT 200MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC2M32B2P-5:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOP
• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 4.5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 280mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 4.5 ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Current State
precharging
precharge)
precharge)
activating,
(with auto
(with auto
precharge
precharge
active, or
disabled)
disabled)
Write
Write
(auto
(auto
Read
Read
Row
Any
Idle
Truth Table 4 – Current State Bank n, Command to Bank m
Notes 1–6 apply to entire table; notes appear below and on next page
Notes:
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
1. This table applies when CKE
2. This table describes an alternate bank operations, except where noted; that is, the current
3. Current state definitions:
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
after
state is for bank n and the commands shown are those allowed to be issued to bank m
(assuming that bank m is in such a state that the given command is allowable). Exceptions
are covered in the notes below.
Idle:
Row active:
Read:
Write:
Read w/auto
precharge enabled:
Write w/auto
precharge enabled:
when all banks are idle.
t
CAS#
XSR has been met (if the previous state was self refresh).
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
WE#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
The bank has been precharged, and
A row in the bank has been activated, and
data bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled and
has not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled and
has not yet terminated or been terminated.
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
n - 1
41
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Command (Action)
t
t
RP has been met. After
RP has been met. After
n
is HIGH (see Table 8 on page 38) and
t
RP has been met.
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
t
RCD has been met. No
t
t
RP is met, the bank
RP is met, the bank
Commands
7, 8, 14
7, 8, 15
7, 8, 16
7, 8, 17
Notes
7, 10
7, 11
7, 12
7, 13
7
7
9
9
9
9