MT48LC2M32B2P-5:G Micron Technology Inc, MT48LC2M32B2P-5:G Datasheet - Page 9

• Manufacturer Part Number: MT48LC2M32B2P-5:G
• Description: IC SDRAM 64MBIT 200MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC2M32B2P-5:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOP
• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 4.5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 280mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 4.5 ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
2, 4, 5, 7, 8, 10,
11, 13, 74, 76,
77, 79, 80, 82,
83, 85, 31, 33,
34, 36, 37, 39,
40, 42, 45, 47,
48, 50, 51, 53,
25–27, 60–66,
16, 71, 28, 59
86-Pin TSOP
Numbers
17, 18, 19
22, 23
54, 56
68
67
20
24
Pin/Ball Descriptions
90-Ball VFBGA
P9, M8, M7, L8,
L2, M3, M2, P1,
G1, G2, G3, H1,
R8, N7, R9, N8,
N2, R1, N3, R2,
E8, D7, D8, B9,
C8, A9, C7, A8,
A2, C3, A1, C2,
G8, G9, F7, F3,
B1, D2, D3, E2
K9, K1, F8, F2
Numbers
H2, J3, G7
K8, K7, J9
J7, H8
J1
J2
J8
BA0, BA1
Symbol
A0–A10
DQM0–
DQM3
CAS#,
DQ0–
DQ31
WE#,
RAS#
CLK
CKE
CS#
Output
Input/
Input
Input
Input
Input
Input
Input
Input
Type
Clock: CLK is driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CLK. CLK also increments
the internal burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides PRECHARGE power-
down and SELF REFRESH operation (all banks idle), ACTIVE
power-down (row active in any bank), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during
power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH, but READ/WRITE bursts
already in progress will continue and DQM operation will retain
its DQ mask capability while CS# is HIGH. CS# provides for
external bank selection on systems with multiple banks. CS# is
considered part of the command code.
Command inputs: WE#, CAS#, and RAS# (along with CS#)
define the command being entered.
Input/output mask: DQM is sampled HIGH and is an input
mask signal for write accesses and an output enable signal for
read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (2-clock latency)
during a READ cycle. DQM0 corresponds to DQ0–DQ7; DQM1
corresponds to DQ8–DQ15; DQM2 corresponds to DQ16–DQ23;
and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 are
considered same state when referenced as DQM.
Bank address input(s): BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs: A0–A10 are sampled during the ACTIVE
command (row-address A0–A10) and READ/WRITE command
(column-address A0–A7 with A10 defining auto precharge) to
select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to
determine whether all banks are to be precharged (A10 HIGH)
or bank selected by BA0, BA1 (LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
Data I/Os: Data bus.
9
Pin/Ball Assignments and Descriptions
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM