MT45W1MW16PDGA-70 IT TR Micron Technology Inc, MT45W1MW16PDGA-70 IT TR Datasheet - Page 5

• Manufacturer Part Number: MT45W1MW16PDGA-70 IT TR
• Description: IC PSRAM 16MBIT 70NS 48VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16PDGA-70 IT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFBGA
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
Functional Block Diagram
Figure 2:
PDF: 09005aef81cadc83/Source:09005aef81c6edb4
16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN
WE#
OE#
UB#
CE#
LB#
ZZ#
Functional Block Diagram – 1 Meg x 16
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Note:
Control
Logic
Micron
oped for low-power, portable applications. The MT45W1MW16PD is a 16Mb DRAM core
device organized as 1 Meg x 16 bits. These devices include the industry-standard, asyn-
chronous memory interface found on other low-power SRAM or pseudo-SRAM offer-
ings.
A user-accessible configuration register (CR) defines how the CellularRAM device per-
forms on-chip refresh and whether page mode read accesses are permitted. This register
is automatically loaded with a default setting during power-up and can be updated at
any time during normal operation.
To operate seamlessly on an asynchronous memory bus, CellularRAM products incor-
porate a transparent self-refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on device
read/write performance.
Special attention has been focused on current consumption during self refresh. Cellular-
RAM products include three system-accessible mechanisms to minimize refresh cur-
rent. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the
refresh rate to match the device temperature. The refresh rate decreases at lower tem-
peratures to minimize current consumption during standby. TCR can also be set by the
system for maximum device temperatures of +85°C, +45°C, and +15°C. Setting sleep
enable (ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or
deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that
contains essential data. DPD halts refresh operation altogether and is used when no vital
information is stored in the device. These three refresh mechanisms are accessed
through the CR.
Functional block diagrams illustrate simplified device operation. See truth table, ball
descriptions, and timing diagrams for detailed information.
®
CellularRAM™ products are high-speed, CMOS PSRAM memory devices devel-
Address Decode
Configuration
16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory
Register (CR)
Logic
5
1,024K x 16
Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DRAM
Array
Output
Buffers
Input/
MUX
and
General Description
©2005 Micron Technology, Inc. All rights reserved.
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