MT48LC8M16A2P-75:G Micron Technology Inc, MT48LC8M16A2P-75:G Datasheet - Page 42

• Manufacturer Part Number: MT48LC8M16A2P-75:G
• Description: IC SDRAM 128MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M16A2P-75:G

• Memory Type: SDRAM
• Format - Memory: RAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Memory Configuration: 16M X 8
• Access Time: 5.4ns
• Page Size: 128Mbit
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 9:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Row active
precharge
precharge
disabled)
disabled)
Current
(Aauto
State
Write
(auto
Read
Any
Idle
Truth Table 3 – Current State Bank n, Command to Bank n
Notes: 1–6; notes appear below and on next page
CS#
Notes:
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
1. This table applies when CKE
2. This table is bank-specific, except where noted; that is, the current state is for a specific
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
after
bank, and the commands shown are those allowed to be issued to that bank when in that
state. Exceptions are covered in the notes below.
Idle:
Row active:
Read:
Write:
MAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Truth Table 3 and according to Truth Table 4.
Precharging:
Row activating:
Read w/auto
precharge enabled:
Write w/auto
precharge enabled:
t
CAS#
XSR has been met (if the previous state was self refresh).
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
The bank has been precharged, and
A row in the bank has been activated, and
bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has not
yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has not
yet terminated or been terminated.
WE#
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
Starts with registration of a PRECHARGE command and ends when
t
Starts with registration of an ACTIVE command and ends when
is met. After
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
RP is met. After
Command (Action)
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LMR
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start precharge)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start precharge)
BURST TERMINATE
n - 1
42
was HIGH and CKE
t
RCD is met, the bank will be in the row active state.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, the bank will be in the idle state.
t
t
RP has been met. After
RP has been met. After
n
t
RP has been met.
is HIGH (see Table 8 on page 41) and
128Mb: x4, x8, x16 SDRAM
t
RCD has been met. No data
©1999 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank
RP is met, the bank
Operations
Notes
11
10
10
10
10
10
10
7
7
8
8
9
8
9
t
RCD