MT48LC16M8A2P-75:G Micron Technology Inc, MT48LC16M8A2P-75:G Datasheet

IC SDRAM 128MBIT 133MHZ 54TSOP

MT48LC16M8A2P-75:G

Manufacturer Part Number
MT48LC16M8A2P-75:G
Description
IC SDRAM 128MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC16M8A2P-75:G

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (16M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
16Mx8
Density
128Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SDRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site:
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive edge
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge, and
• Self refresh mode; standard and low power
• 64ms, 4,096-cycle refresh (commercial & industrial)
• 16ms, 4,096-cycle refresh (Automotive)
• LVTTL-compatible inputs and outputs
• Single +3.3 ±0.3V power supply
Notes:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_1.fm - Rev. N 1/09 EN
Options
• Configurations
• Write recovery (
• Package/Pinout
• Timing (cycle time)
• Self refresh
• Design revision
• Operating temperature range
of system clock
changed every clock cycle
auto refresh modes
– 32 Meg x 4 (8 Meg x 4 x 4 banks)
– 16 Meg x 8 (4 Meg x 8 x 4 banks)
– 8 Meg x 16 (2 Meg x 16 x 4 banks)
– Plastic package – OCPL
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free
– 60-ball FBGA (8mm x 16mm)
– 60-ball FBGA (8mm x 16mm) Pb-free
– 54-ball VFBGA (8mm x 8mm)
– 54-ball VFBGA (8mm x 8mm) Pb-free
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
– 6.0ns @ CL = 3 (x16 only)
– Standard
– Low power
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
t
WR = “2 CLK”
1. Refer to Micron technical note: TN-48-05.
2. Off-center parting line.
3. Consult Micron for availability.
4. x16 only.
Products and specifications discussed herein are subject to change by Micron without notice.
t
WR)
1
2
Designator
32M4
16M8
8M16
None
None
BB
FB
B4
-6A
AT
F4
-75
-7E
TG
IT
A2
:G
P
L
3
4
4
3
3
3
www.micron.com
1
Figure 1:
Notes:
Table 1:
Table 2:
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
Speed
Grade
-6A
-7E
-7E
-75
-75
DQ0
DQ1
x4
NC
NC
NC
NC
NC
NC
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1. The # symbol indicates signal is active LOW. A dash (-) indicates
DQ0
DQ1
DQ2
DQ3
x8
NC
NC
NC
NC
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x8 and x4 pin function is same as x16 pin function.
Frequency
DQML
x16
V
V
CAS#
RAS#
167 MHz
143 MHz
133 MHz
133 MHz
100 MHz
VssQ
VssQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
WE#
BA0
BA1
DD
DD
A10
V
V
CS#
V
Clock
A0
A1
A2
A3
DD
DD
DD
Q
Q
Address Table
Key Timing Parameters
CL = CAS (Read) latency
54-Pin TSOP Pin Assignment
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
8 Meg x 4 x 4
4 (BA0, BA1)
32 Meg x 4
4K (A0–A11)
2K (A0–A9,
128Mb: x4, x8, x16 SDRAM
banks
A11)
4K
CL = 2
5.4ns
6ns
Access Time
©1999 Micron Technology, Inc. All rights reserved.
CL = 3
4 Meg x 8 x 4
4K (A0–A11)
4 (BA0, BA1)
5.4ns
5.4ns
5.4ns
16 Meg x 8
1K (A0–A9)
banks
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
4K
Setup
Time
x16
Vss
DQ15
VssQ
DQ14
DQ13
V
DQ12
DQ11
VssQ
DQ10
DQ9
V
DQ8
Vss
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
DD
DD
Q
Q
2 Meg x 16 x 4
Features
4K (A0–A11)
4 (BA0, BA1)
8 Meg x 16
512 (A0–A8)
x8
-
DQ7
-
NC
DQ6
-
NC
DQ5
-
NC
DQ4
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
banks
4K
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
Hold
Time
0.8ns
0.8ns
0.8ns
0.8ns
0.8ns
x4
-

Related parts for MT48LC16M8A2P-75:G

MT48LC16M8A2P-75:G Summary of contents

Page 1

SDRAM MT48LC32M4A2 – 8 Meg banks MT48LC16M8A2 – 4 Meg banks MT48LC8M16A2 – 2 Meg banks For the latest data sheet, refer to Micron’s Web site: Features • ...

Page 2

... Table 3: 128Mb SDRAM Part Numbers Part Number MT48LC32M4A2TG MT48LC32M4A2P MT48LC16M8A2TG MT48LC16M8A2P MT48LC16M8A2FB MT48LC16M8A2BB MT48LC8M16A2TG MT48LC8M16A2P MT48LC8M16A2B4 MT48LC8M16A2F4 Notes: 1. FBGA Device Decode: http://www.micron.com/support/FBGA/FBGA.asp General Description The Micron containing 134,217,728 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’ ...

Page 3

Automotive Temperature The automotive temperature (AT) option adheres to the following specifications: • 16ms refresh rate • Self refresh not supported • Ambient and case temperature cannot be less than –40°C or greater than +105°C PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_1.fm - ...

Page 4

Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

List of Figures Figure 1: 54-Pin TSOP Pin Assignment (Top View ...

Page 6

Figure 57: 60-Ball FBGA “FB/BB” Package (x8 device), 8mm x 16mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7

List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 8

FBGA Ball Assignments Figure 2: 60-Ball FBGA Ball Assignments (Top View), 16 Meg x 8, 8mm x 16mm PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N ...

Page 9

Figure 3: 54-Ball VFBGA Assignments (Top View), 8 Meg x 16, 8mm x 8mm Notes: 1. The balls at A4, A5, and A6 are not in the physical package. They are ...

Page 10

... A0–A11, ADDRESS 14 BA0, BA1 REGISTER 11 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev BANK0 ROW- 12 ROW- ADDRESS ADDRESS MUX MEMORY 4,096 LATCH & (4,096 x 2,048 x 4) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC 2 COLUMN ...

Page 11

... A0–A11, ADDRESS 14 BA0, BA1 REGISTER 10 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev BANK0 ROW- 12 ROW- ADDRESS ADDRESS MUX MEMORY 4,096 LATCH & (4,096 x 1,024 x 8) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC 2 COLUMN ...

Page 12

... A0–A11, ADDRESS 14 BA0, BA1 REGISTER 9 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev BANK0 ROW- 12 ADDRESS ROW- ADDRESS MUX MEMORY 4,096 LATCH & (4,096 x 512 x 16) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC 2 COLUMN ...

Page 13

... A0–A11) and READ/WRITE command (column-address A0–A9, A11 [x4]; A0–A9 [x8]; A0–A8 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (A10 [LOW]) ...

Page 14

Table 4: Pin/Ball Descriptions (Continued) 54-Ball 60-Ball 54-Pin TSOP VFBGA FBGA A8, B9, B8, 10, 11, 13, C9, C8, D9, 42, 44, 45, D8, E9, E1, 47, 48, 50, D2, D1, C2, 51, 53 C1, ...

Page 15

Functional Description In general, the 128Mb SDRAMs (8 Meg banks, 4 Meg banks, and 2 Meg banks) are quad-bank DRAMs that operate at 3.3V and include a synchronous ...

Page 16

Wait at least given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least are allowed. 10. Issue an AUTO REFRESH command. 11. ...

Page 17

When a READ or WRITE command is issued, a block of columns equal to the BL is effec- tively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if ...

Page 18

Figure 7: Mode Register Definition A11, A10 = “0, 0” to ensure compatibility with future devices. Write Burst Mode A9 0 Programmed Burst Length 1 Single Location Access A8 A7 A6–A0 Operating Mode 0 0 Defined Standard Operation – – ...

Page 19

Table 5: Burst Definition Burst Length Full page (y) Notes: 1. For full-page accesses 2,048 (x4 1,024 (x8), and y = 512 (x16). 2. For A1–A9, A11 (x4), A1–A9 (x8), ...

Page 20

Table 6: CAS Latency Figure 8: CAS Latency COMMAND COMMAND Operating Mode The normal operating mode is selected by setting M7 and the other combina- tions of values for M7 and M8 are reserved for future use ...

Page 21

Commands Table 7 provides a quick reference of available commands. This is followed by a written description of each command. Three additional truth tables appear following “Opera- tions” on page 24; these tables provide current state/next state information. Table 7: ...

Page 22

... Input data appearing on the DQ is written to the memory array subject to the DQM input logic level appearing coin- cident with the data given DQM signal is registered LOW, the corresponding data will be written to memory ...

Page 23

A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is ...

Page 24

The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. After CKE ...

Page 25

Figure 9: Activating a Specific Row in a Specific Bank A0–A10, A11 BA0, BA1 Figure 10: Example: Meeting CLK COMMAND Reads READ bursts are initiated with a READ command, as shown in Figure 11 on page 26. The starting column ...

Page 26

Figure 11: READ Command A0–A9, A11: x4 A0–A9: x8 A0–A8: x16 A9, A11: x16 Figure 12: CAS Latency COMMAND COMMAND PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN CLK CKE HIGH CS# RAS# CAS# WE# COLUMN ADDRESS A11: x8 ...

Page 27

Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be ...

Page 28

Figure 14: Random READ Accesses COMMAND ADDRESS COMMAND ADDRESS Notes: 1. Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length ...

Page 29

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 15 shows the case where the clock frequency allows for bus ...

Page 30

This is shown in Figure 17 for each possible CL; data element either the last of a burst of four or the last desired of ...

Page 31

Figure 18: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS Notes: 1. DQM is LOW. WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 19 on page 32. The starting column and bank addresses are provided ...

Page 32

Figure 19: WRITE Command A0–A9, A11: x4 A0–A9: x8 A0–A8: x16 A9, A11: x16 Figure 20: WRITE Burst COMMAND ADDRESS Notes DQM is LOW. Data for any WRITE burst may be truncated with a subsequent WRITE ...

Page 33

A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 22 on page 33, ...

Page 34

Figure 23: WRITE-to-READ COMMAND ADDRESS Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not acti- vated), and a full-page WRITE burst may be ...

Page 35

Figure 24: WRITE-to-PRECHARGE CLK ≥ 15ns DQM COMMAND ADDRESS CLK < 15ns DQM COMMAND ADDRESS Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length ...

Page 36

PRECHARGE The PRECHARGE command (see Figure 26) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subse- quent row access some specified time ( ...

Page 37

Figure 27: Power-Down CLK CKE COMMAND All banks idle Enter power-down mode Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered low. In the clock suspend mode, the internal clock is ...

Page 38

Figure 29: Clock Suspend During READ Burst INTERNAL CLOCK COMMAND ADDRESS Notes: 1. For this example greater, and DQM is LOW. BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming ...

Page 39

Figure 30: READ With Auto Precharge Interrupted by a READ CLK COMMAND BANK n Internal States BANK m ADDRESS DQ Notes: 1. DQM is LOW. Figure 31: READ With Auto Precharge Interrupted by a WRITE CLK READ - AP COMMAND ...

Page 40

Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after valid data WRITE to bank n will be ...

Page 41

Table 8: Truth Table 2 – CKE Notes: 1–4 CKE CKE Current State Power-down Self refresh Clock suspend L H Power-down Self refresh Clock suspend H L All banks idle All banks idle Reading ...

Page 42

Table 9: Truth Table 3 – Current State Bank n, Command to Bank n Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle ...

Page 43

The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Accessing mode register: Precharging all: 6. All states and sequences not ...

Page 44

Table 10: Truth Table 4 – Current State Bank n, Command to Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle X X Row L L activating, L ...

Page 45

A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m ...

Page 46

Electrical Specifications Stresses greater than those listed in Table 11 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...

Page 47

Table 12: Temperature Limits Parameter Operating case temperature: Commercial Industrial Automotive Junction temperature: Commercial Industrial Automotive Ambient temperature: Commercial Industrial Automotive Peak reflow temperature Notes: 1. MAX operating case temperature, T side of the device, as shown in Figure 34, ...

Page 48

Figure 34: Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point Figure 35: Example Temperature Test Point Location, 54-Ball VFBGA: Top View Test point Figure 36: Example Temperature Test Point Location, 60-Ball FBGA: Top View Test point PDF: ...

Page 49

Table 14: DC Electrical Characteristics and Operating Conditions Notes notes appear on page 51; V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Input leakage current: Any input ...

Page 50

Table 17: Electrical Characteristics and Recommended AC Operating Conditions Notes 11; notes appear on page 51 Characteristics AC Parameter Access time from CLK (positive edge Address hold time Address setup ...

Page 51

Table 18: AC Functional Characteristics Notes 11; notes appear on page 51 Parameter DQM to data mask during WRITEs DQM to data High-Z during READs WRITE command to input data delay Data-in to ACTIVE command ...

Page 52

Other input signals are allowed to transition no more than once every 2 clocks and are otherwise at valid V 13 14. Timing actually specified by cycle rate. 15. Timing actually specified by minimum cycle rate. 16. ...

Page 53

Timing Diagrams Figure 37: Initialize and Load Mode Register CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ...

Page 54

Figure 38: Power-Down Mode CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two ...

Page 55

Figure 39: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM / DQML, DQMH ...

Page 56

Figure 40: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ ...

Page 57

Figure 41: Self Refresh Mode T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High ...

Page 58

Figure 42: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ROW ...

Page 59

Figure 43: READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE ...

Page 60

Figure 44: Single READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ...

Page 61

Figure 45: Single READ – With CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMU A0–A9, A11 ROW ROW A10 ...

Page 62

Figure 46: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE AUTO ...

Page 63

Figure 47: READ – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 ...

Page 64

Figure 48: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE AUTO ...

Page 65

Figure 49: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH A0–A9, A11 COLUMN m ...

Page 66

Figure 50: WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0–A9, ...

Page 67

Figure 51: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMU A0–A9, A11 ROW ...

Page 68

Figure 52: Single WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW t ...

Page 69

Figure 53: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0–A9, A11 ...

Page 70

Figure 54: WRITE – Full-Page Burst CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 ...

Page 71

Figure 55: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 t AS ...

Page 72

Package Dimensions Figure 56: 54-Pin Plastic TSOP (400 mil) PIN # 0. 1.00 10.16 ±0.08 11.76 ±0.20 +0.03 0.15 -0.02 Notes: 1. All dimensions in millimeters. 2. Package width and length do not include mold ...

Page 73

Figure 57: 60-Ball FBGA “FB/BB” Package (x8 device), 8mm x 16mm 0.155 ±0.013 0.850 ±0.05 60X Ø 0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. PRE- REFLOW DIAMETER IS 0. 0.33 NSMD BALL PAD. BALL A8 8.00 ±0.05 ...

Page 74

Figure 58: 54-Ball VFBGA “F4/B4” Package (x16 device), 8mm x 8mm 0.65 ±0.05 SEATING PLANE C 0.10 C 54X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS 0.42. BALL A9 6.40 3.20 3.20 ...

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