MT48LC16M8A2P-75:G Micron Technology Inc, MT48LC16M8A2P-75:G Datasheet - Page 19

IC SDRAM 128MBIT 133MHZ 54TSOP

MT48LC16M8A2P-75:G

Manufacturer Part Number
MT48LC16M8A2P-75:G
Description
IC SDRAM 128MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC16M8A2P-75:G

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (16M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
16Mx8
Density
128Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC16M8A2P-75:G
Manufacturer:
ST
Quantity:
2 000
Part Number:
MT48LC16M8A2P-75:G
Manufacturer:
MICRON/美光
Quantity:
230
Table 5:
CAS Latency
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Burst Definition
Notes:
1. For full-page accesses: y = 2,048 (x4), y = 1,024 (x8), and y = 512 (x16).
2. For BL = 2, A1–A9, A11 (x4), A1–A9 (x8), or A1–A8 (x16) select the block-of-two burst; A0
3. For BL = 4, A2–A9, A11 (x4), A2–A9 (x8), or A2–A8 (x16) select the block-of-four burst; A0–
4. For BL = 8, A3–A9, A11 (x4), A3–A9 (x8), or A3–A8 (x16) select the block-of-eight burst; A0–
5. For a full-page burst, the full row is selected and A0–A9, A11 (x4), A0–A9 (x8), or A0–A8
6. Whenever a boundary of the block is reached within a given sequence above, the following
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be set to 2 or 3 clocks.
If a READ command is registered at clock edge n and the latency is m clocks, the data will
be available by clock edge n + m. The DQ will start driving as a result of the clock edge 1
cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will
be valid by clock edge n + m. For example, assuming that the clock cycle time is such that
all relevant access times are met, if a read command is registered at T0 and the latency is
programmed to 2 clocks, the DQ will start driving after T1 and the data will be valid by
T2, as shown in Figure 8 on page 20. Table 6 on page 20 indicates the operating frequen-
cies at which each CL setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Full page
Length
Burst
selects the starting column within the block.
A1 select the starting column within the block.
A2 select the starting column within the block.
(x16) select the starting column.
access wraps within the block.
(y)
2
4
8
A2
Starting Column
0
0
0
0
1
1
1
1
n = A0–A11/9/8
(location 0–y)
Address
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
19
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Cn, Cn + 1, Cn + 2,
Cn + 3, Cn + 4...,
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
...Cn - 1, Cn
Order of Accesses Within a Burst
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
128Mb: x4, x8, x16 SDRAM
Functional Description
©1999 Micron Technology, Inc. All rights reserved.
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0

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