ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 25

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

Data Sheet
CURRENT SHARING
The
digital current sharing. The
information for current sharing (this setting is programmed
in Register 0x29[3]).
Analog Current Sharing
Analog current sharing uses the internal current sensing
circuitry to provide a current reading to an external current
error amplifier. Therefore, an additional differential current
amplifier is not necessary.
The current reading from CS2 can be output to the SHAREo
pin in the form of a digital bit stream, which is the output of the
current sense ADC (see Figure 33). The bit stream from the Σ-Δ
ADC is proportional to the current delivered by this unit to the
load. By filtering this digital bit stream using an external RC filter,
the current information is turned into an analog voltage that is
proportional to the current delivered by this unit to the load. This
voltage can be compared to the share bus voltage. If the unit is not
supplying enough current, an error signal can be applied to the
VS3± feedback point. This signal causes the unit to increase its
output voltage and, in turn, its current contribution to the load.
Digital Share Bus
The digital share bus scheme is similar in principle to the tradi-
tional analog share bus scheme. The difference is that instead of
using a voltage on the share bus to represent current, a digital
word is used.
The
digital word is a function of the current that the power supply is
providing (the higher the current, the larger the digital word).
The power supply with the highest current controls the bus
(master). A power supply that is putting out less current (slave)
sees that another supply is providing more power to the load
than it is.
ADP1046A
ADP1046A
supports both analog current sharing and
outputs a digital word onto the share bus. The
PREVIOUS
2 STOP BITS
FRAME
ADP1046A
(IDLE)
CS2+
CURRENT
CURRENT
SENSE
ADC
START BIT
uses the CS2 current
0
CS2–
Figure 34. Digital Current Share Frame Timing Diagram
BIT STREAM
Figure 33. Analog Current Share Configuration
SHARE
BUS
Rev. 0 | Page 25 of 88
8-BIT DATA
FRAME
SHAREo
During the next cycle, the slave increases its current output contri-
bution by increasing its output voltage. This cycle continues until
the slave outputs the same current as the master, within a pro-
grammable tolerance range. Figure 32 shows the configuration
of the digital share bus.
The digital share bus is based on a single-wire communication
bus principle; that is, the clock and data signals are contained
together.
When two or more
chronize their share bus timing. This synchronization is performed
by the start bit at the beginning of a communications frame. If a
new
bus, the device waits to begin sharing until the next frame. The
new
which designates the end of a share frame. It then performs
synchronization with the other
next start bit. The digital share bus frame is shown in Figure 34.
BIT STREAM
ADP1046A
ADP1046A
CURRENT SENSE
CURRENT SENSE
POWER SUPPLY A
POWER SUPPLY B
INFO
INFO
Figure 32. Digital Current Share Configuration
2 STOP BITS
LPF
is hot-swapped onto an existing digital share
monitors the share bus until it sees a stop bit,
(IDLE)
ADP1046A
VOLTAGE
DIGITAL
DIGITAL
WORD
WORD
START BIT
NEXT FRAME
0
ADP1046A
devices are connected, they syn-
SHAREo
SHAREo
SHAREi
SHAREi
devices during the
ADP1046A
SHARE
BUS
V
DD