MT48LC32M8A2P-7E:D Micron Technology Inc, MT48LC32M8A2P-7E:D Datasheet - Page 40

IC SDRAM 256MBIT 133MHZ 54TSOP

MT48LC32M8A2P-7E:D

Manufacturer Part Number
MT48LC32M8A2P-7E:D
Description
IC SDRAM 256MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC32M8A2P-7E:D

Package / Case
54-TSOP II
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (32M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
RoHS Compliant
Memory Case Style
TSOP
No. Of Pins
54
Operating Temperature Range
0°C To +70°C
Operating Temperature Max
70°C
Operating Temperature Min
0°C
Organization
32Mx8
Density
256Mb
Address Bus
15b
Access Time (max)
5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Memory Configuration
4 BLK (8M X 8)
Interface Type
LVTTL
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 18: Truth Table – Current State Bank n, Command to Bank m
Notes 1–6 apply to all parameters and conditions
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Current State
Any
Idle
Row activating, active, or
precharging
Read
(auto precharge disabled)
Write
(auto precharge disabled)
Read
(with auto precharge)
Write
(with auto precharge)
Notes:
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted; for example, the cur-
3. Current state definitions:
after
rent state is for bank n and the commands shown can be issued to bank m, assuming
that bank m is in such a state that the given command is supported. Exceptions are cov-
ered below.
Idle: The bank has been precharged, and
Row active: A row in the bank has been activated, and
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
RAS# CAS# WE# Command/Action
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
t
XSR has been met (if the previous state was self refresh).
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise supported for bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
40
n-1
was HIGH and CKE
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP has been met.
256Mb: x4, x8, x16 SDRAM
n
is HIGH (Table 19 (page 42)), and
t
RCD has been met. No data bursts/
© 1999 Micron Technology, Inc. All rights reserved.
Truth Tables
7, 8, 14
7, 8, 15
7, 8, 16
7, 8, 17
Notes
7, 10
7, 11
7, 12
7, 13
7
7
9
9
9
9

Related parts for MT48LC32M8A2P-7E:D