MT48LC32M8A2P-7E:D Micron Technology Inc, MT48LC32M8A2P-7E:D Datasheet - Page 49

• Manufacturer Part Number: MT48LC32M8A2P-7E:D
• Description: IC SDRAM 256MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC32M8A2P-7E:D

• Package / Case: 54-TSOP II
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (8M X 8)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 20: Burst Definition Table
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Burst Length
Continuous
2
4
8
n = A0–An/9/8 (location 0–y)
Starting Column Address
A2
0
0
0
0
1
1
1
1
Notes:
1. For full-page accesses: y = 2,048 (x4); y = 1,024 (x8); y = 512 (x16).
2. For BL = 2, A1–A9, A11 (x4); A1–A9 (x8); or A1–A8 (x16) select the block-of-two burst; A0
3. For BL = 4, A2–A9, A11 (x4); A2–A9 (x8); or A2–A8 (x16) select the block-of-four burst; A0–
4. For BL = 8, A3–A9, A11 (x4); A3–A9 (x8); or A3–A8 (x16) select the block-of-eight burst;
5. For a full-page burst, the full row is selected and A0–A9, A11 (x4); A0–A9 (x8); or A0–A8
6. Whenever a boundary of the block is reached within a given sequence above, the follow-
7. For BL = 1, A0–A9, A11 (x4); A0–A9 (x8); or A0–A8 (x16) select the unique column to be
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
selects the starting column within the block.
A1 select the starting column within the block.
A0–A2 select the starting column within the block.
(x16) select the starting column.
ing access wraps within the block.
accessed, and mode register bit M3 is ignored.
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1,
Type = Sequential
49
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn...
0-1
1-0
Order of Accesses Within a Burst
Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 SDRAM
© 1999 Micron Technology, Inc. All rights reserved.
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
Mode Register
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0