MT48LC32M8A2P-7E:D Micron Technology Inc, MT48LC32M8A2P-7E:D Datasheet - Page 55

IC SDRAM 256MBIT 133MHZ 54TSOP

MT48LC32M8A2P-7E:D

Manufacturer Part Number
MT48LC32M8A2P-7E:D
Description
IC SDRAM 256MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC32M8A2P-7E:D

Package / Case
54-TSOP II
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (32M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
RoHS Compliant
Memory Case Style
TSOP
No. Of Pins
54
Operating Temperature Range
0°C To +70°C
Operating Temperature Max
70°C
Operating Temperature Min
0°C
Organization
32Mx8
Density
256Mb
Address Bus
15b
Access Time (max)
5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Memory Configuration
4 BLK (8M X 8)
Interface Type
LVTTL
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 23: READ-to-WRITE
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 23
(page 55) shows where, due to the clock cycle frequency, bus contention is avoided
without having to add a NOP cycle, while Figure 24 (page 56) shows the case where an
additional NOP cycle is required.
A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-
mand to the same bank, provided that auto precharge was not activated. The PRE-
CHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 25 (page 56) for
each possible CL; data element n + 3 is either the last of a burst of four or the last de-
sired data element of a longer burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until
the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or continuous
page bursts.
Command
Address
1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
DQM
CLK
DQ
to any bank. If a burst of one is used, DQM is not required.
T0
Col n
READ
Bank,
T1
NOP
Transitioning data
T2
NOP
55
T3
NOP
D
t HZ
OUT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t CK
Don’t Care
T4
WRITE
Col b
Bank,
D
IN
t
DS
256Mb: x4, x8, x16 SDRAM
t
RP is met. Note that part of
© 1999 Micron Technology, Inc. All rights reserved.
READ Operation

Related parts for MT48LC32M8A2P-7E:D