MT48LC32M8A2P-7E:D Micron Technology Inc, MT48LC32M8A2P-7E:D Datasheet - Page 57

• Manufacturer Part Number: MT48LC32M8A2P-7E:D
• Description: IC SDRAM 256MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC32M8A2P-7E:D

• Package / Case: 54-TSOP II
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (8M X 8)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 26: Terminating a READ Burst
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
Continuous-page READ bursts can be truncated with a BURST TERMINATE command
and fixed-length READ bursts can be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 26 (page 57) for each possible CAS
latency; data element n + 3 is the last desired data element of a longer burst.
Command
Command
1. DQM is LOW.
Address
Address
CLK
CLK
DQ
DQ
Bank,
T0
Col n
T0
READ
Bank,
READ
Col n
CL = 2
CL = 3
T1
T1
NOP
NOP
57
T2
T2
NOP
NOP
D
OUT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
D
D
OUT
OUT
TERMINATE
TERMINATE
BURST
BURST
T4
T4
X = 1 cycle
D
D
256Mb: x4, x8, x16 SDRAM
OUT
OUT
Transitioning data
X = 2 cycles
T5
T5
NOP
NOP
D
D
OUT
OUT
© 1999 Micron Technology, Inc. All rights reserved.
T6
T6
READ Operation
NOP
NOP
D
OUT
Don’t Care
T7
NOP