MT48LC32M8A2P-7E:D Micron Technology Inc, MT48LC32M8A2P-7E:D Datasheet - Page 70

• Manufacturer Part Number: MT48LC32M8A2P-7E:D
• Description: IC SDRAM 256MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC32M8A2P-7E:D

• Package / Case: 54-TSOP II
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (8M X 8)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 39: READ With Auto Precharge Interrupted by a READ
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Internal
states
Command
Note:
Address
Bank m
Bank n
CLK
DQ
registered. The last valid data WRITE to bank n will be data registered one clock prior to
a WRITE to bank m (see Figure 46 (page 76)).
1. DQM is LOW.
Page active
NOP
T0
READ - AP
Page active
Bank n,
Bank n
T1
Col a
READ with burst of 4
T2
CL = 3 (bank n)
NOP
70
READ - AP
Bank m,
T3
Bank m
Col d
Interrupt burst, precharge
READ with burst of 4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T4
CL = 3 (bank m)
NOP
t
RP - bank n
D
OUT
T5
NOP
256Mb: x4, x8, x16 SDRAM
D
OUT
PRECHARGE Operation
T6
NOP
D
© 1999 Micron Technology, Inc. All rights reserved.
OUT
Idle
T7
Don’t Care
NOP
t RP - bank m
D
Precharge
OUT