MT46V64M8P-6T:F Micron Technology Inc, MT46V64M8P-6T:F Datasheet - Page 43

• Manufacturer Part Number: MT46V64M8P-6T:F
• Description: IC DDR SDRAM 512MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V64M8P-6T:F

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Organization: 64Mx8
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 175mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Table 28:
Table 29:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Function
DESELECT
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column and start READ burst)
WRITE (select bank and column and start WRITE burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(enter self refresh mode)
LOAD MODE REGISTER
Name (Function)
Write enable
Write inhibit
Truth Table 1 – Commands
CKE is HIGH for all commands shown except SELF REFRESH; All states and sequences not shown are illegal or
reserved
Truth Table 2 – DM Operation
Used to mask write data, provided coincident with the corresponding data
Notes:
Tables 28 and 29 provide a quick reference of available commands. Two additional Truth
Tables—Table 30 on page 44 and Table 31 on page 45—provide current state/next state
information.
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A0–An (128Mb: n = 11; 256Mb and 512Mb: n = 12; 1Gb:
3. BA0–BA1 provide bank address; A0–Ai provide column address, (where Ai is the most signif-
4. Applies only to READ bursts with auto precharge disabled; this command is undefined (and
5. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are pre-
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing while in self refresh mode, all inputs and
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
n = 13) provide row address.
icant column address bit for a given density and configuration, see Table 2 on page 2) A10
HIGH enables the auto precharge feature (non persistent), and A10 LOW disables the auto
precharge feature.
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
charged and BA0–BA1 are “Don’t Care.”
I/Os are “Don’t Care” except for CKE.
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-
tions of BA0–BA1 are reserved). A0–An provide the op-code to be written to the selected
mode register.
DM
43
H
L
CS#
H
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
H
H
H
H
X
L
L
L
L
512Mb: x4, x8, x16 DDR SDRAM
CAS#
X
H
H
H
H
L
L
L
L
WE#
H
H
H
H
X
L
L
L
L
©2000 Micron Technology, Inc. All rights reserved.
Valid
DQ
Bank/row
Address
X
Bank/col
Bank/col
Op-code
Code
X
X
X
X
Commands
Notes
6, 7
1
1
2
3
3
4
5
8