MT48LC4M32B2P-6:G Micron Technology Inc, MT48LC4M32B2P-6:G Datasheet - Page 33

• Manufacturer Part Number: MT48LC4M32B2P-6:G
• Description: IC SDRAM 128MBIT 167MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2P-6:G

• Package / Case: 86-TSOPII
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 86
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 195mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (1M X 32)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 24:
Clock Suspend
Figure 25:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
Power-Down
CLOCK SUSPEND During WRITE Burst
Notes:
COMMAND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 22 on page 31 and Figure 23 on page 32.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
COMMAND
1. For this example, BL = 4 or greater, and DM is LOW.
CLK
CKE
INTERNAL
ADDRESS
CLOCK
All banks idle
Enter power-down mode.
CKE
CLK
D
IN
t CKS
NOP
T0
NOP
BANK,
WRITE
COL n
D
T1
n
IN
Input buffers gated off
T2
33
(
(
(
(
)
(
)
)
)
)
(
(
(
(
)
(
)
)
)
)
T3
Exit power-down mode.
NOP
n + 1
T4
D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IN
> t CKS
DON’T CARE
T5
NOP
n + 2
D
NOP
IN
DON’T CARE
ACTIVE
t RCD
t RAS
t RC
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition