MT48LC4M32B2P-6:G Micron Technology Inc, MT48LC4M32B2P-6:G Datasheet - Page 36

• Manufacturer Part Number: MT48LC4M32B2P-6:G
• Description: IC SDRAM 128MBIT 167MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2P-6:G

• Package / Case: 86-TSOPII
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 86
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 195mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (1M X 32)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 29:
Figure 30:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
WRITE With Auto Precharge Interrupted by a READ
WRITE With Auto Precharge Interrupted by a WRITE
Notes:
Notes:
1. DQM is LOW.
1. DQM is LOW.
Internal
States
Internal
States
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
CLK
DQ
DQ
Page Active
Page Active
T0
NOP
T0
NOP
WRITE - AP
WRITE - AP
BANK n,
BANK n,
Page Active
Page Active
BANK n
BANK n
COL a
COL a
T1
T1
D
D
a
a
IN
IN
WRITE with Burst of 4
WRITE with Burst of 4
36
a + 1
a + 1
T2
T2
D
D
NOP
NOP
IN
IN
BANK m,
READ - AP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
a + 2
T3
COL d
T3
BANK m
D
NOP
IN
Interrupt Burst, Write-Back
t
WR - BANK n
READ with Burst of 4
BANK m,
WRITE - AP
COL d
T4
T4
BANK m
CL = 3 (BANK m)
D
NOP
t
d
IN
Interrupt Burst, Write-Back
WR - BANK n
WRITE with Burst of 4
T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
RP - BANK n
T6
T6
d + 2
D
NOP
D
NOP
OUT
t RP - BANK n
d
IN
Precharge
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
DON’T CARE
DON’T CARE
T7
T7
d + 3
D
d + 1
NOP
NOP
D
t WR - BANK m
OUT
t RP - BANK m
IN
Write-Back