MT48H16M16LFBF-75:H Micron Technology Inc, MT48H16M16LFBF-75:H Datasheet - Page 50

SDRAM 256M-BIT 1.8V 54-PIN VFBGA

MT48H16M16LFBF-75:H

Manufacturer Part Number
MT48H16M16LFBF-75:H
Description
SDRAM 256M-BIT 1.8V 54-PIN VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet

Specifications of MT48H16M16LFBF-75:H

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
256M (16Mx16)
Speed
132MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
8/6ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
80mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4707290

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Figure 19: READ-to-WRITE
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
Note:
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 19
(page 50) shows where, due to the clock cycle frequency, bus contention is avoided
without having to add a NOP cycle, while Figure 20 (page 51) shows the case where an
additional NOP cycle is required.
A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-
mand to the same bank, provided that auto precharge was not activated. The PRE-
CHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 21 (page 51) for
each possible CL; data element n + 3 is either the last of a burst of four or the last de-
sired data element of a longer burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until
the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or continuous
page bursts.
Command
Address
1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
DQM
CLK
DQ
to any bank. If a burst of one is used, DQM is not required.
T0
Col n
READ
Bank,
T1
NOP
Transitioning data
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
T2
NOP
50
T3
NOP
D
t HZ
OUT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t CK
Don’t Care
T4
WRITE
Col b
Bank,
D
IN
t
DS
t
RP is met. Note that part of
©2008 Micron Technology, Inc. All rights reserved.
READ Operation

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