MT48LC4M32B2TG-7:G Micron Technology Inc, MT48LC4M32B2TG-7:G Datasheet - Page 39

• Manufacturer Part Number: MT48LC4M32B2TG-7:G
• Description: IC SDRAM 128MBIT 143MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2TG-7:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOPII
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/8/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 175mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
11. Does not affect the state of the bank and acts as a NOP to that bank.
5. The following states must not be interrupted by any executable command; COMMAND
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
state for precharging.
less of bank.
auto precharge enabled and READs or WRITEs with auto precharge disabled.
Accessing mode
Precharging all: Starts with registration of a PRECHARGE ALL command and ends
Refreshing: Starts with registration of an AUTO REFRESH command and ends
register:
when
banks idle state.
Starts with registration of a LOAD MODE REGISTER command and
ends when
be in the all banks idle state.
when
39
t
t
RFC is met. Once
RP is met. Once
t
MRD has been met. Once
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, all banks will be in the idle state.
t
RFC is met, the SDRAM will be in the all
t
MRD is met, the SDRAM will
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition