MT48LC4M32B2TG-7:G Micron Technology Inc, MT48LC4M32B2TG-7:G Datasheet - Page 40

• Manufacturer Part Number: MT48LC4M32B2TG-7:G
• Description: IC SDRAM 128MBIT 143MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2TG-7:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOPII
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/8/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 175mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 11:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
auto precharge)
auto precharge)
Row activating,
Current State
precharging
Write (auto
Write (with
Read (auto
Read (with
precharge
precharge
active, or
disabled)
disabled)
Any
Idle
Truth Table – CURRENT STATE BANK n, COMMAND TO BANK m
Notes 1–6 apply to the entire table; notes appear below and on next page
Notes:
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted; i.e., the current state is
3. Current state definitions:
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
H
H
H
H
H
H
H
H
X
X
H
H
H
L
L
L
L
L
L
L
L
L
L
after
for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
when all banks are idle.
represented by the current state only.
Precharge Enabled:
Precharge Enabled:
CAS#
t
XSR has been met (if the previous state was self refresh).
H
H
H
H
X
X
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
Write w/Auto
Read w/Auto
Row Active: A row in the bank has been activated, and
WE# COMMAND (ACTION)
X
H
X
H
H
H
H
H
H
H
H
H
H
Write: A WRITE burst has been initiated, with auto precharge disabled, and
L
L
L
L
L
L
L
L
L
L
Read: A READ burst has been initiated, with auto precharge disabled, and
Idle: The bank has been precharged, and
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
data bursts/accesses and no register accesses are in progress.
has not yet terminated or been terminated.
has not yet terminated or been terminated.
Starts with registration of a READ command with auto precharge
enabled, and ends when
bank will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled, and ends when
bank will be in the idle state.
n-1
40
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RP has been met. Once
RP has been met. Once
n
is HIGH (see Table 9 on page 37) and
t
RP has been met.
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
t
RCD has been met. No
t
t
RP is met, the
RP is met, the
7, 8, 14
7, 8, 15
7, 8, 16
7, 8, 17
Notes
7, 10
7, 11
7, 12
7, 13
7
7
9
9
9
9