MT48V8M16LFB4-8:G Micron Technology Inc, MT48V8M16LFB4-8:G Datasheet - Page 31

IC SDRAM 128MBIT 125MHZ 54VFBGA

MT48V8M16LFB4-8:G

Manufacturer Part Number
MT48V8M16LFB4-8:G
Description
IC SDRAM 128MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr

Specifications of MT48V8M16LFB4-8:G

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
2.5V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
100mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48V8M16LFB4-8:G
Manufacturer:
MICRON
Quantity:
4 000
Part Number:
MT48V8M16LFB4-8:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48V8M16LFB4-8:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 16:
Figure 17:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
READ-to-WRITE
READ-to-WRITE with Extra Clock Cycle
Notes:
Notes:
COMMAND
1. CL = 3 is used for illustration.
2. The READ command may be to any bank, and the WRITE command may be to any bank.
3. If a burst of 1 is used, then DQM is not required.
The DQM input is used to avoid I/O contention, as shown in Figure 16 and Figure 17.
The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE command
(DQM latency is 2 clocks for output buffers) to suppress data-out from the READ. After
the WRITE command is registered, the DQ will go High-Z (or remain High-Z), regardless
of the state of the DQM signal, provided the DQM was active on the clock just prior to
the WRITE command that truncated the READ command. If not, the second WRITE will
be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 17, then the
WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
0 clocks for input buffers) to ensure that the written data is not masked. Figure 16 shows
the case where the clock frequency allows for bus contention to be avoided without
adding a NOP cycle, and Figure 17 shows the case where the additional NOP is needed.
COMMAND
1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-
ADDRESS
ADDRESS
mand may be to any bank.
DQM
DQM
CLK
CLK
DQ
DQ
BANK,
COL n
T0
BANK,
T0
COL n
READ
READ
TRANSITIONING DATA
T1
T1
NOP
NOP
T2
T2
TRANSITIONING DATA
NOP
NOP
31
T3
T3
NOP
NOP
D
t HZ
OUT
D
t HZ
OUT
t CK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
n
DON’T CARE
T4
BANK,
COL b
T4
WRITE
NOP
D
IN
128Mb: x16, x32 Mobile SDRAM
b
t
DS
DON’T CARE
T5
BANK,
COL b
WRITE
D
IN
b
t
DS
©2001 Micron Technology, Inc. All rights reserved.
READs

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