MT48V8M16LFB4-8:G Micron Technology Inc, MT48V8M16LFB4-8:G Datasheet - Page 35

IC SDRAM 128MBIT 125MHZ 54VFBGA

MT48V8M16LFB4-8:G

Manufacturer Part Number
MT48V8M16LFB4-8:G
Description
IC SDRAM 128MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr

Specifications of MT48V8M16LFB4-8:G

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
2.5V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
100mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48V8M16LFB4-8:G
Manufacturer:
MICRON
Quantity:
4 000
Part Number:
MT48V8M16LFB4-8:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48V8M16LFB4-8:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
WRITEs
Figure 20:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
WRITE Command
WRITE bursts are initiated with a WRITE command, as shown in Figure 20.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge either is enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the WRITE
commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQ will remain High-Z, and any additional input
data will be ignored (see Figure 21 on page 36). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0 and continue.)
x16: A0–A8
x32: A0–A7
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 21 on page 36. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipe-
lined architecture and, therefore, does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 22 on page 36, or each subsequent WRITE may be
performed to a different bank.
A9, A11
BA0,1
RAS#
CAS#
WE#
CLK
CKE
A10
CS#
HIGH
VALID ADDRESS
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ADDRESS
ADDRESS
COLUMN
BANK
35
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile SDRAM
©2001 Micron Technology, Inc. All rights reserved.
READs

Related parts for MT48V8M16LFB4-8:G