MT46V64M16P-6T IT:A TR Micron Technology Inc, MT46V64M16P-6T IT:A TR Datasheet - Page 47
![IC DDR SDRAM 1GBIT 6NS 66TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT46V64M16P-6T IT:A TR
Manufacturer Part Number
MT46V64M16P-6T IT:A TR
Description
IC DDR SDRAM 1GBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16P-6T IT:A TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Burst Length (BL)
Burst Type
Table 28:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Burst Length
2
4
8
Burst Definition
Starting Column Address
A2
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
1
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length
being programmable for both READ and WRITE bursts, as shown in Figure 21 on
page 46. The burst length determines the maximum number of column locations that
can be accessed for a given READ or WRITE command. BL = 2, BL = 4, or BL = 8 locations
are available for both the sequential and the interleaved burst types. Reserved states
should not be used, as unknown operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block—
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–Ai when BL = 2, by A2–Ai when BL = 4, and by A3–Ai when
BL = 8 (where Ai is the most significant column address bit for a given configuration).
The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. For example: for BL = 8, A3–Ai select the eight-data-element block; A0–
A2 select the first access within the block.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 28.
A1
A1
–
–
–
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
47
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
–
–
–
Order of Accesses Within a Burst
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR SDRAM
Type = Interleaved
©2003 Micron Technology, Inc. All rights reserved.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
–
–
–
Operations