M25P40-VMP6TG NUMONYX, M25P40-VMP6TG Datasheet - Page 23
![IC FLASH 4MBIT 50MHZ 8VFQFPN](/photos/18/97/189768/3778330_sml.jpg)
M25P40-VMP6TG
Manufacturer Part Number
M25P40-VMP6TG
Description
IC FLASH 4MBIT 50MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P40-VMP6G.pdf
(61 pages)
Specifications of M25P40-VMP6TG
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Memory Configuration
512K X 8
Ic Interface Type
Serial, SPI
Clock Frequency
50MHz
Supply Voltage Range
2.3V To 3.6V
Memory Case Style
VDFPN
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P40-VMP6TG
Manufacturer:
st
Quantity:
11 116
Part Number:
M25P40-VMP6TG
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P40-VMP6TG-X
Manufacturer:
STM
Quantity:
12 000
Part Number:
M25P40-VMP6TG-X
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P40-VMP6TG/TE
Manufacturer:
ST
Quantity:
2 000
6.4.3
6.4.4
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer accepted for execution.
Figure 10. Read Status Register (RDSR) instruction sequence and data-out
S
C
D
Q
sequence
0
High Impedance
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
Status Register Out
9 10 11 12 13 14 15
5
4
3
2
1
0
MSB
7
6
Status Register Out
5
Table
4
3
2) becomes
2
1
0
7
AI02031E
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