M25PE40-VMC6G NUMONYX, M25PE40-VMC6G Datasheet

no-image

M25PE40-VMC6G

Manufacturer Part Number
M25PE40-VMC6G
Description
IC SRL FLSH 4MB 75MHZ 8MLP
Manufacturer
NUMONYX
Series
Forté™r
Datasheet

Specifications of M25PE40-VMC6G

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-MLP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25PE40-VMC6G
Manufacturer:
Micron Technology Inc.
Quantity:
366
Features
January 2008
SPI bus compatible serial interface
4 Mbit page-erasable Flash memory
Page size: 256 bytes
– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)
Subsector Erase (4 Kbytes)
Sector Erase (64 Kbytes)
Bulk Erase (4 Mbits)
2.7 V to 3.6 V single supply voltage
75 MHz clock rate (maximum)
Deep Power-down mode 1 µA (typical)
Electronic signature
– JEDEC standard two-byte signature
Software write protection on a 64-Kbyte sector
basis
Hardware write protection of the memory area
selected using the BP0, BP1 and BP2 bits
More than 100 000 Write cycles
More than 20 year data retention
Packages
– ECOPACK® (RoHS compliant)
(8013h)
byte alterability, 75 MHz SPI bus, standard pinout
4 Mbit, page-erasable serial Flash memory with
Rev 9
SO8W (MW) 208 mils
SO8N (MN) 150 mils
6 × 5 mm (MLP8)
VFQFPN8 (MP)
M25PE40
www.numonyx.com
1/62
1

Related parts for M25PE40-VMC6G

M25PE40-VMC6G Summary of contents

Page 1

... BP0, BP1 and BP2 bits More than 100 000 Write cycles More than 20 year data retention Packages – ECOPACK® (RoHS compliant) January 2008 4 Mbit, page-erasable serial Flash memory with Rev 9 M25PE40 VFQFPN8 (MP) 6 × (MLP8) SO8W (MW) 208 mils SO8N (MN) 150 mils www.numonyx.com 1/62 1 ...

Page 2

... Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13 4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8.1 4.8.2 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 2/62 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Specific hardware and software protections . . . . . . . . . . . . . . . . . . . . . 15 M25PE40 ...

Page 3

... M25PE40 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Write Status Register (WRSR 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Read Lock Register (RDLR 6.9 Page Write (PW 6.10 Page Program (PP 6.11 Write to Lock Register (WRLR ...

Page 4

... Table 26. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . 57 Table 27. SO8W – 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . 58 Table 28. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 29. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4/62 Important note on page M25PE40 ...

Page 5

... M25PE40 List of figures Figure 1. Logic diagram - previous T7X process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Logic diagram - new T9HX process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8 ...

Page 6

... Description 1 Description The M25PE40 Mbit (512Kbit × 8 bit) serial paged Flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle ...

Page 7

... Top Sector Lock or Write Protect Reset Supply voltage Ground Figure 1 and Figure 2). M25PE40 TSL for package dimensions, and how to identify pin-1. Logic diagram - new T9HX process M25PE40 W Reset V SS Direction Input Input Output Input Input Input Reset AI09703d Description Q AI13781 7/62 ...

Page 8

... When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance. Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. 8/62 M25PE40 ...

Page 9

... M25PE40 2.6 Write Protect (W) or Top Sector Lock (TSL) The Write Protect function is available in the T9HX process only (see note on page The Write Protect (W) input is used to freeze the size of the area of memory that is protected against write, program and erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register ...

Page 10

... Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25PE40 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...

Page 11

... M25PE40 Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA µs <=> the application must ensure that the Bus MSB SPI modes MSB AI01438B 11/62 ...

Page 12

... Page Write (PW) sequences with each containing only a few bytes (see Table 21: AC characteristics (50 MHz operation, T9HX (0.11µm) characteristics (75 MHz operation, T9HX (0.11µm) 12/62 Section 6.9: Page Write (PW), process), and Table 22: AC process)). M25PE40 ...

Page 13

... M25PE40 4.3 A fast way to modify data The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to ‘1’. This might be: when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier Page Erase (PE) or Sector Erase (SE) instruction ...

Page 14

... PUW (WRSR), (PP), Section 6.12: Page Erase Section 6.13: Subsector Erase pulse. Section 6.4: Read Status Register (RDSR) ) can provide protection against inadvertent Section 6.9: Page Write (PW), (PE), Section 6.14: Sector (SSE), and to Table 12: Device status after M25PE40 ...

Page 15

... M25PE40 4.8.2 Specific hardware and software protections The M25PE40 features a Hardware Protected mode, HPM, and two Software Protected modes, SPM1 and SPM2 that can be combined to protect the memory array as required. They are described below: HPM HPM in T7X process (see The Hardware Protected mode (HPM) is entered when Top Sector Lock (TSL) is driven Low, causing the top 256 pages of memory to become read-only ...

Page 16

... All sectors (eight sectors All sectors (eight sectors All sectors (eight sectors All sectors (eight sectors Protection status Unprotected area (1) All sectors (eight sectors Lower seven-eighths (seven sectors Lower three-quarters (six sectors Lower half (four sectors none none none none M25PE40 ...

Page 17

... M25PE40 5 Memory organization The memory is organized as: 2048 pages (256 bytes each) 524,288 bytes (8 bits each) 128 subsectors (32 Kbits, 4096 bytes each) 8 sectors (512 Kbits, 65536 bytes each) Each page can be individually: – programmed (bits are programmed from – erased (bits are erased from – ...

Page 18

... High Voltage Generator Status 256 byte Register Data Buffer 7FFFFh Top 256 pages can be made read-only by using the TSL pin Whole memory array can be made read-only on a 64-Kbyte basis through the Lock Registers 000FFh X Decoder M25PE40 (1) AI13782 ...

Page 19

... M25PE40 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input (D), each bit being latched on the rising edges of Serial Clock (C) ...

Page 20

... Important note on page M25PE40 Addr Dummy Data bytes bytes bytes 06h 04h 9Fh ...

Page 21

... M25PE40 6.1 Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page Program (PP), Page Erase (PE), and Sector Erase (SE) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High ...

Page 22

... Write to Lock Register (WRLR) instruction completion Page Erase (PE) instruction completion Subsector Erase (SSE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Figure 8. Write Disable (WRDI) instruction sequence 22/62 (Figure 8) resets the Write Enable Latch (WEL) bit Instruction D High Impedance AI03750D M25PE40 ...

Page 23

... M25PE40 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (80h), and the memory capacity of the device in the second byte (13h) ...

Page 24

... WIP is automatically set and reset by the internal logic of the device). 2. SRWD = Status Register Write Protect bit; BP0, BP1, BP2 = Block Protect bits. 3. The BP bits and the SRWD bit exist only in the T9HX process. 24/62 Figure 10. (1)(2)(3) 0 BP2 BP1 M25PE40 Table 3) becomes b0 BP0 WEL WIP ...

Page 25

... M25PE40 Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Instruction Status Register Out MSB Instructions Status Register Out MSB 7 AI02031E 25/62 ...

Page 26

... The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Note: The Status Register BPi and SRWD bits are available in the M25PE40 in the T9HX process only. See Important note on page 6 Before the Write Status Register (WRSR) instruction can be accepted, a Write Enable (WREN) instruction must previously have been executed ...

Page 27

... M25PE40 Table 8. Protection modes (T9HX process only, see W SRWD signal bit protected 1 1 Hardware 0 1 protected 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 3. The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...

Page 28

... Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence 0 1 High Impedance 1. Address bits A23 to A19 are Don’t care. 28/62 Figure 12 Instruction 24-bit address MSB Data Out MSB M25PE40 Data Out 2 7 AI03748D ...

Page 29

... M25PE40 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...

Page 30

... Instructions 6.8 Read Lock Register (RDLR) Note: The Read Lock Register (RDLR) instruction is decoded only in the M25PE40 in the T9HX process (see Important note on page The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector (or subsector) ...

Page 31

... M25PE40 6.9 Page Write (PW) The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...

Page 32

... Instructions Figure 15. Page Write (PW) instruction sequence MSB 1. Address bits A23 to A19 are Don’t care ≤ n ≤ 256. 32/ Instruction 24-bit address MSB Data byte 2 Data byte MSB Data byte MSB Data byte MSB M25PE40 AI04045 ...

Page 33

... M25PE40 6.10 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...

Page 34

... Instructions Figure 16. Page Program (PP) instruction sequence MSB 1. Address bits A23 to A19 are Don’t care ≤ n ≤ 256. 34/ Instruction 24-bit address MSB Data byte 2 Data byte MSB Data byte MSB Data byte MSB M25PE40 AI04044 ...

Page 35

... M25PE40 6.11 Write to Lock Register (WRLR) Note: The Write to Lock Register (WRLR) instruction is decoded only in the M25PE40 in the T9HX process (see Important note on page The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed ...

Page 36

... Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 18. Page Erase (PE) instruction sequence Address bits A23 to A19 are Don’t care. 36/62 Figure 18 Instruction 24-bit address 23 22 MSB M25PE40 ) is initiated AI04046 ...

Page 37

... M25PE40 6.13 Subsector Erase (SSE) Note: The Subsector Erase (SSE) instruction is decoded only in the M25PE40 in the T9HX process (see Important note on page The Subsector Erase (SSE) instruction sets to ‘1’ (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed ...

Page 38

... Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 20. Sector Erase (SE) instruction sequence Address bits A23 to A19 are Don’t care. 38/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 20 Instruction 23 22 MSB 24-bit address AI03751D M25PE40 ) is ...

Page 39

... Bulk Erase (BE) Note: The Bulk Erase (BE) instruction is decoded only in the M25PE40 in the T9HX process (see Important note on page The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...

Page 40

... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 22. Deep Power-down (DP) instruction sequence 40/62 Table 17). Figure 22 Instruction M25PE40 before the supply current is reduced Standby mode Deep Power-down mode to CC1 AI03753D ...

Page 41

... M25PE40 6.17 Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (D) ...

Page 42

... WI VSL modes. – all operations are disabled, and WI threshold. However, the correct WI is still below (min), the device can be CC delay is not yet fully elapsed. M25PE40 is less CC has PUW (min). No supply. CC ...

Page 43

... M25PE40 Figure 24. Power-up timing (max) Program, Erase and Write commands are rejected by the device Chip selection not allowed V CC (min) Reset state of the device V WI Table 11. Power-up timing and V Symbol ( (min low VSL CC (1) t Time delay before the first Write, Program or Erase instruction ...

Page 44

... S remains Low while Reset is Low. 44/62 Lock bits status (1) : WREN, Reset to ‘0’ Reset to ‘0’ Reset to ‘0’ Reset to ‘0’ M25PE40 Internal logic Addressed data status Same as POR Not significant Equivalent to Addressed data POR could be modified Equivalent to ...

Page 45

... M25PE40 9 Initial delivery state The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte contains FFh). All usable Status Register bits are 0. 10 Maximum rating Stressing the device above the rating listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...

Page 46

... Input levels 0.8V CC 0.2V CC (1) Parameter Test condition V OUT °C and a frequency of 25 MHz. A Min. Max. 2.7 3.6 –40 85 Min. Max 0. 0. Input and output timing reference levels 0.7V CC 0.3V CC AI00825B Min. Max M25PE40 Unit V °C Unit Unit pF pF ...

Page 47

... M25PE40 Table 17. DC characteristics Symbol Parameter I Input Leakage current LI I Output Leakage current LO Standby current I CC1 (Standby and Reset modes) I Deep Power-down current CC2 Operating current I CC3 (FAST_READ) I Operating current (PW) CC4 I Operating current (SE) CC5 V Input Low voltage IL V Input High voltage ...

Page 48

... When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256). 48/62 Table 14 and Table 15 Parameter Min. D.C. D.C. 100 100 . C M25PE40 Typ. Max. Unit 25 MHz 20 MHz 0.1 V/ns ...

Page 49

... M25PE40 Table 20. AC characteristics (33 MHz operation) 33 MHz only available for products marked since week 40 of 2005 Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PW, PP, PE, SE, DP, RDP, WREN WRDI, RDSR f Clock frequency for READ instructions R ( Clock High time ...

Page 50

... A. For instance, int(12/ int(32/ int(15.3) =16. 50/62 Table 14 Parameter Min. D.C. D.C. 0.1 100 100 . C (1) (2) ) and Table 15 Typ. Max 8 0.8 3 (7) int(n/8) × 0.025 150 8 10 Section 13: Ordering M25PE40 Unit MHz MHz µs µ ...

Page 51

... M25PE40 Table 22. AC characteristics (75 MHz operation, T9HX (0.11µm) process Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, RDLR, PW, PP, WRLR, PE, SE SSE, DP, RDP, WREN, WRDI, RDSR, WRSR f Clock frequency for READ instructions R ( Clock High time CH CLH ...

Page 52

... Figure 27. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold timing TSL or W tTHSL tWHSL High Impedance Q 1. For the differences between devices produced in the two processes, see 52/62 tSLCH tCHSH tCHDX tCLCH MSB IN tSHSL tSHCH tCHCL LSB IN AI01447C tSHTL tSHWL Important note on page 6. M25PE40 AI3559 ...

Page 53

... M25PE40 Figure 28. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tCH tCLQV tQLQH tQHQL DC and AC parameters tCL tSHQZ LSB OUT AI01449e 53/62 ...

Page 54

... Under completion of an Erase cycle of an SSE operation Under completion of a WRSR operation Device deselected (S High) and in Standby mode tSHRH tRLRH Table 14 Table 15 and Min. Typ (1)(2) Table 14 Table 15 and Max. (3) : WREN, 30 300 3 t (see W Table 0 tRHSL M25PE40 Max. Unit µs ns Unit µs µ 21) µs AI06808 ...

Page 55

... M25PE40 12 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

Page 56

... VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead 6 × 5 mm, package mechanical data (continued) Symbol L Θ aaa bbb ddd 56/62 millimeters Typ Min Max 0.60 0.50 0.75 12° 0.15 0.10 0.05 M25PE40 inches Typ Min Max 0.024 0.020 0.029 12° 0.006 0.004 0.002 ...

Page 57

... M25PE40 Figure 31. SO8N – 8 lead plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 26. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc ccc millimeters Typ Min Max 1.75 0.10 ...

Page 58

... inches Typ Min 0.000 0.059 0.016 0.014 0.008 0.004 0.198 0.300 0.050 – 0° 0.020 8 M25PE40 6L_ME Max 0.098 0.010 0.079 0.020 0.014 0.004 0.238 0.245 0.350 – 10° 0.031 ...

Page 59

... Package only available for products in the T9HX process. Note: For a list of available options (speed, package, etc.), for further information on any aspect of this device or when ordering parts operating at 75 MHz (0.11 µm, process digit ‘4’), please contact your nearest Numonyx Sales Office. M25PE40 (1) Ordering information ...

Page 60

... Document status RHSL Section 4.6: Active modes. scheme. operation). Document Table 19: updated. Section 4.2: An Section 4.3: A fast way to modify and Section 6.10: Page Program (PP) scheme. Added Table 19 and Table 20; amended title and added a footnote; Table 28: Ordering M25PE40 data, ...

Page 61

... M25PE40 Table 29. Document revision history (continued) Date 15-Jan-2007 23-Jan-2007 10-Dec-2007 03-Jan-2007 Revision 50 MHz frequency added. SO8N package added, VFQFPN and SO8W package specifications updated (see mechanical). The sectors are further divided up into subsectors (see Memory organization). Bus master and memory devices on the SPI bus explanatory paragraph added ...

Page 62

... Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 62/62 Please Read Carefully: applications. visiting Numonyx's website at http://www.numonyx.com. Copyright © 11/5/7, Numonyx B.V. All Rights Reserved. M25PE40 ...

Related keywords