M25P40-VMN3PB NUMONYX, M25P40-VMN3PB Datasheet

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M25P40-VMN3PB

Manufacturer Part Number
M25P40-VMN3PB
Description
IC FLASH 4MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheets

Specifications of M25P40-VMN3PB

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Package / Case
SO-8
Cell Type
NOR
Density
4Mb
Access Time (max)
15ns
Interface Type
Serial (SPI)
Address Bus
1b
Operating Supply Voltage (typ)
2.5/3.3V
Operating Temp Range
-40C to 125C
Package Type
SO N
Program/erase Volt (typ)
2.3 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Automotive
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
512K
Supply Current
8mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
April 2010
– JEDEC standard two-byte signature
– Unique ID code (UID) with 16 bytes read-
– RES instruction, one-byte, signature (12h),
– RoHS compliant
4 Mbit of Flash memory
2.3 V to 3.6 V single supply voltage
SPI bus compatible serial interface
75 MHz clock rate (maximum)
Page Program (up to 256 bytes) in 0.8 ms
(typical)
Sector Erase (512 Kbit) in 0.6 s (typical)
Bulk Erase (4 Mbit) in 4.5 s (typical)
Deep Power-down mode 1 µA (typical)
Hardware Write Protection: protected area
size defined by three non-volatile bits (BP0,
BP1 and BP2)
Electronic signatures
Packages
Automotive grade parts available
(2013h)
only, available upon customer request
for backward compatibility
Numonyx
®
4 Mbit, low voltage, serial Flash memory
Forté™ Serial Flash Memory
Rev 20
150 mils width
with 75 MHz SPI bus interface
(MLP8 2 x 3 mm)
SO8 (MN)
MLP8 6 x 5 mm
UFDFPN8 (MB)
DFN8 (MS)
(MLP8 4 x 3 mm)
208 mils width
UFDFPN8 (MC)
(MLP8 6 x 5 mm)
SO8W (MW)
VFDFPN8 (MP)
M25P40
www.Numonyx.com
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M25P40-VMN3PB Summary of contents

Page 1

... Automotive grade parts available April 2010 ® Forté™ Serial Flash Memory 4 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface SO8 (MN) 150 mils width DFN8 (MS) MLP8 UFDFPN8 (MB) (MLP8 mm) Rev 20 M25P40 SO8W (MW) 208 mils width VFDFPN8 (MP) (MLP8 mm) UFDFPN8 (MC) (MLP8 mm) 1/61 www.Numonyx.com 1 ...

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... Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 12 4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 12 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR) ...

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SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 8. Power-up timing and V Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 10. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 11. ...

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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO and MLP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 ...

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... Description The M25P40 Mbit (512 K × 8) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25P40 features high performance instructions allowing clock frequency MHz. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction ...

Page 7

... Supply voltage CC V Ground SS Figure 2. SO and MLP8 connections 1. There is an exposed central pad on the underside of the MLP8 packages. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Section 11: Package mechanical Function M25P40 HOLD ...

Page 8

... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). ...

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V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC 9/61 ...

Page 10

... Bus Master leaves the SPI bus in high impedance. 10/ SPI Memory R R Device S W HOLD Figure 3) ensure that the M25P40 is not selected if requirement is met). The typical value 100K Ω, assuming SHCH (C = parasitic capacitance of the bus line) is shorter than the p p Figure 4, is the clock polarity when the ...

Page 11

Example pF, that is R*C p never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA ...

Page 12

... Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...

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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P40 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...

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... To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. 14/61 Memory content Protected area none Upper eighth (Sector 7) ...

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Figure 5. Hold condition activation C HOLD (standard use) Hold Condition (non-standard use) Hold Condition AI02029D 15/61 ...

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... Memory organization The memory is organized as: 524,288 bytes (8 bits each) 8 sectors (512 Kbits, 65,536 bytes each) 2048 pages (256 bytes each) Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...

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... Figure 6. Block diagram HOLD W Control Logic Address Register and Counter High Voltage Generator I/O Shift Register 256 Byte Data Buffer 7FFFFh 00000h 000FFh 256 Bytes (Page Size) X Decoder Status Register Size of the read-only memory area AI04986 17/61 ...

Page 18

... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. ...

Page 19

Table 4. Instruction set Instruction WREN Write Enable WRDI Write Disable (1) RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase ...

Page 20

Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...

Page 21

... Device identification (2 bytes) Unique ID code (UID) (17 bytes, 16 which are available upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (13h). ...

Page 22

... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. ...

Page 23

... Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set ...

Page 24

Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...

Page 25

... Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification ...

Page 26

... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...

Page 27

... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...

Page 28

... Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...

Page 29

Figure 14. Page Program (PP) instruction sequence Instruction Data Byte ...

Page 30

Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...

Page 31

Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...

Page 32

Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the ...

Page 33

... Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data output (Q), the 8-bit Electronic Signature, whose value for the M25P40 is 12h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release ...

Page 34

... Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P40, is 12h. Figure 19. Release from Deep Power-down instruction sequence Instruction D High Impedance Q 34/ Dummy Bytes ...

Page 35

Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...

Page 36

Figure 20. Power-up timing (max (min) Reset State of the Device V WI Table 8. Power-up timing and V Symbol ( (min low VSL CC (1) t Time delay to ...

Page 37

... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 9. ...

Page 38

DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the ...

Page 39

Table 14. DC characteristics (device grade 6) Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating ...

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Table 15. DC characteristics (device grade 3) Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating ...

Page 41

Table 17. Instruction times, process technology 150 nm Test conditions specified in Symbol Alt. t Write Status Register cycle time W — Page Program cycle time (256 bytes) ( — Page Program cycle time (n bytes) t — ...

Page 42

Table 19. AC characteristics (25 MHz operation, device grade 3, V Identified with device belonging to X technology version; Test conditions specified in Symbol Alt. Clock frequency for the following f f instructions: FAST_READ, PP, SE, BE, DP ...

Page 43

Table 20. AC characteristics (50 MHz operation, device grade 6, V Test conditions specified in Symbol Alt. Clock frequency for the following f f instructions: FAST_READ, PP, SE, BE, DP RES, WREN, RDID, WRDI, RDSR, WRSR f Clock ...

Page 44

Table 21. AC characteristics (*40 MHz operation, device grade 6, V Symbol Alt — ( CLH ( CLL (2) t — CLCH (2) t — CHCL t t ...

Page 45

Table 22. AC characteristics, 75 MHz operation, VCC min = 2.7 V Applies only to products made with 110 nm technology, identified with process digit ‘4’ and process letter “B” in the part number Test conditions specified in Symbol Alt. ...

Page 46

Details of how to find the technology process in the marking are given in AN1995, see also Ordering Information, Standard 2. 75 MHz operation is available only on the VCC range 2 3.6 V; the maximum frequency ...

Page 47

Figure 24. Hold timing HOLD Figure 25. Output timing S C tCLQV tCLQV tCLQX tCLQX Q ADDR. D LSB IN tHLCH tCHHL tCHHH tHLQZ tHHQX tCH tCL tQLQH tQHQL tHHCH AI02032 tSHQZ LSB OUT AI01449e 47/61 ...

Page 48

Package mechanical 40 MHz is the maximum frequency for the devices operation in the extended Vcc range 2 2.7 V. Figure 26. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, package outline A2 ...

Page 49

Figure 27. SO8W – 8 lead plastic small outline, 208 mils body width, package outline Drawing is not to scale. Table 24. SO8 wide – 8 lead plastic small outline, 208 mils body width, ...

Page 50

Figure 28. DFN8 (MLP8) 8-lead, dual flat package no lead, 6 × 5 mm, package outline Drawing is not to scale. Table 25. DFN8 (MLP8) 8-lead dual flat package no lead ...

Page 51

Figure 29. VFDFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 × 5 mm, package outline 0. 0. Drawing is not to ...

Page 52

Figure 30. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead package mechanical data 1. Drawing is not to scale. 52/61 ...

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Table 27. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead package mechanical data Databook (mm) Symbol Typ Min A 0.55 0.45 A1 0.02 0.00 A3 — 0.127 θ — D2 0.80 0.70 ...

Page 54

Figure 31. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead package outline Drawing is not to scale. Table 28. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package ...

Page 55

... Letter, please refer to AN1995: Serial Flash Memory Device Marking or contact your nearest Numonyx Sales Office. Note: For available options (speed, package, etc.) or for further information on this device, please contact your nearest Numonyx Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard Example:M25P40 – ...

Page 56

JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 56/61 ...

Page 57

... Tested Parts from the non Auto Tested parts). Note: Numonyx strongly recommends the use of the Automotive Grade devices (Auto Grade 6 and automotive envirnoment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your Numonyx sales office for a copy. M25P40 – ...

Page 58

... Revision 12-Apr-2001 1.0 Document written. 25-May-2001 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory. Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection modes; Release from Power-down and Read Electronic Signature (RES); Power- up. 11-Sep-2001 1.2 Repositioning of several tables and illustrations without changing their contents. ...

Page 59

... Removed “AC characteristics (33 MHz operation, device grade 6, VCCmin =2.3 V)” Table. Modified the note below 26-Jun-2007 14 Changed test condition for I Changed clock frequency, from MHz, in 10-Dec-2007 15 Added Numonyx Branding. Changed frequency MHz (only in the standard Vcc range). Added new packages. 15-Oct-2008 16 Added UID/CFD protection. Extended Vcc range to 2.3 V. Changes 2 ...

Page 60

Table 31. Document revision history (continued) Date Revision Revised the following: – Table 8: Vwi Min (Grade vs. 2.1V or (remove one row & Grade indication) – Table 11: Erase/Program cycles = 100000 cycles also for Grade ...

Page 61

... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...

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