LH28F640SPHT-PTL12 Sharp Microelectronics, LH28F640SPHT-PTL12 Datasheet
LH28F640SPHT-PTL12
Specifications of LH28F640SPHT-PTL12
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LH28F640SPHT-PTL12 Summary of contents
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
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... TSOP (Normal Bend) Pinout ....................... 3 Pin Descriptions.......................................................... 4 CE0, CE1, CE2 Truth Table ....................................... 5 Memory Map .............................................................. 6 Identifier Codes Address ............................................ 7 OTP Block Address Map............................................ 8 Bus Operation............................................................. 9 Command Definitions .............................................. 10 Functions of Block Lock .......................................... 12 Status Register Definition......................................... 13 Extended Status Register Definition ........................ 14 STS Configuration Definition .................................. 15 LHF64P01 CONTENTS PAGE 1 Electrical Specifications ...
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... The block locking scheme is available for memory array and this scheme provides maximum flexibility for safe nonvolatile code and data storage. OTP (One Time Program) block provides an area to store security code and to protect its code. * ETOX is a trademark of Intel Corporation. LHF64P01 LH28F640SPHT-PTL12 64Mbit (4Mbit 16/8Mbit 8) Page Mode Flash MEMORY Enhanced Data Protection Features • Individual Block Lock • ...
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... Addresses are internally latched during an erase or a program cycle. DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code, INPUT/ DQ -DQ identifier code reads. Data pins float to high-impedance (High Z) when the chip or ...
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NOTE: 1. For single-chip applications, CE LHF64P01 Table Truth Table ...
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... Block 3 030000 460000 02FFFF 45FFFF 64-Kword/128-Kbyte Block 2 020000 440000 01FFFF 43FFFF 64-Kword/128-Kbyte Block 1 010000 420000 00FFFF 41FFFF 64-Kword/128-Kbyte Block 0 000000 400000 Figure 2. Memory Map 3FFFFF 3E0000 3DFFFF 3C0000 3BFFFF 3A0000 39FFFF 380000 37FFFF 360000 35FFFF 340000 33FFFF 320000 ...
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Manufacturer Code Manufacturer Code Device Code Device Code Block Lock Configuration Block is Unlocked Code Block is Locked NOTES: 1. The address A don't care "00H" is presented Block Address = The beginning ...
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LHF64P01 [ 000FFFH Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H Reserved for Future Implementation 000080H (DQ -DQ 15 Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP Block ...
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... WE# CE 0,1 Enabled Enabled IH IH Disabled Enabled Enabled Enabled memory contents can be read, but cannot be altered. PEN PENLK or V PENLK and V voltages. PENLK PENH : 16 bit) and DQ IH =2.7V-3.6V. CC (4) V Address DQ PEN OUT X X High High High Z Refer to Refer to X Table 3 Table 3 ...
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... QA=Query codes address. Refer to Appendix of LH28F640SP series for details. BA=Address within the block for block erase, page buffer program or set block lock bit. WA=Address of memory location for the Program command. OA=Address of OTP block to be read or programmed (Refer to Figure 3). 3. The upper byte of the data bus (DQ ID=Data to be read from identifier codes ...
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Refer to Appendix of LH28F640SP series for details both block erase operation and (page buffer) program operation are suspended, the suspended (page buffer) program operation is resumed when writing the Block Erase and (Page Buffer) Program Resume (D0H) ...
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Table 6. Functions of Block Lock (3) State Name Unlocked 1 Locked NOTES: 1. Selected block is locked by the Set Block Lock Bit command. Following the Clear Block Lock Bits command, all the blocks are unlocked ...
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WSMS BESS BECBLS 7 6 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS ...
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SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 =RESERVED FOR FUTURE ENHANCEMENTS (R) ...
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... After power-up or device reset, STS configuration is set to "00". STS configuration 00 The output of the STS pin is the control signal to prevent accessing a flash memory while the internal WSM is busy (SR.7="0"). when the WSM is STS configuration 01 OL The output of the STS pin is the control signal to indicate that the erase operation is completed and the flash memory is available for the next operation ...
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Electrical Specifications 1.1 Absolute Maximum Ratings Operating Temperature During Read, Erase and Program ...- +85 C Storage Temperature During under Bias............................... - +85 C During non Bias................................ - +125 C Voltage On Any ...
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Capacitance ( f=1MHz) A Symbol Parameter C Input Capacitance IN C Output Capacitance OUT NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions V CCQ INPUT 0.0 AC test inputs are driven at ...
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DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Automatic Power Savings Current CCAS Reset Current CCD CC Average V ...
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Symbol Parameter V Block Erase, Clear Block Lock CC I CCE Bits Current I V (Page Buffer) Program or CCWS CC I Block Erase Suspend Current CCES V Input Low Voltage IL V Input High Voltage IH V Output Low ...
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AC Characteristics - Read-Only Operations Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV Output Delay ELQV X t Page Address Access Time APA t OE# to Output Delay GLQV t RP# High ...
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(A) 22 Disabled ( ( Enabled ( OE# ( (W) WE (D/Q) 15 (P) ...
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... IL V High (D/Q) 15 (P) RP ELFH V IH (F) BYTE Figure 7. AC Waveform for 4-Word Page Mode Read Operations NOTE: 1. Memory array supports page mode read operations. LHF64P01 VALID ADDRESS t AVQV VALID VALID ADDRESS ADDRESS t ELQV t GLQV t GLQX t APA t ELQX VALID VALID OUTPUT OUTPUT t ...
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... PHQV V IH (P) RP ELFL V IH (F) BYTE Figure 8. AC Waveform for 8-Byte Page Mode Read Operations NOTE: 1. Memory array supports page mode read operations. LHF64P01 VALID ADDRESS VALID VALID ADDRESS ADDRESS t ELQV t GLQV t GLQX t APA VALID VALID VALID OUTPUT OUTPUT OUTPUT ...
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AC Characteristics - Write Operations Symbol t Write Cycle Time AVAV RP# High Recovery to WE# (CE PHWL PHEL (WE#) Setup to WE# (CE ELWL WLEL WE# (CE ...
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NOTE (A) 22 Disabled ( ( Enabled ( ELWL WLEL V IH OE# ( PHWL PHEL V IH WE# ( ...
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Reset Operations V RP High (D/Q) 15 RP# ( High (D/Q) 15 (min GND V ...
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Block Erase, (Page Buffer) Program and Block Lock Configuration Performance Symbol Page Buffer Program Time (Time to Program 16 words/ 32 bytes WHQV3 Program Time t EHQV3 Block Program Time (Using Page Buffer Program Command ...
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Related Document Information Document No. FUM03201 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. LHF64P01 (1) Document Name LH28F640SP series Appendix 28 Rev. 0.06 ...
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... Table 5. Command Definitions PROBLEM While block erase or (page buffer) program is being suspended by issuing Block Erase and (Page Buffer) Program Suspend command, memory array data can not be normally read by issuing read array command. WORKAROUND Block Erase and (Page Buffer) Program Suspend command should not be issued. ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). See the “DC CHARACTERISTICS“ described in specifications for V (Min.) or ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv 030313 ...